From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9264FC7EE2E for ; Sat, 10 Jun 2023 20:09:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231128AbjFJUJt (ORCPT ); Sat, 10 Jun 2023 16:09:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231748AbjFJUJs (ORCPT ); Sat, 10 Jun 2023 16:09:48 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F047C3598; Sat, 10 Jun 2023 13:09:46 -0700 (PDT) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1686427785; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=VN3pKad915lgXyIEKLmAqU9HFdxhV2U8JR5HtaJJWAo=; b=ZJPuUMqPysjPBQOtwRD8hr8P3yWoBfFxIFRfQbmUhqrHISkVZgbVnK1l0yUcMF13n0ef88 A2mJqnviZJYpqgkQxY2B/Iddyx7txFX0h7NoqsWvq/aS5ZDorHIECmwNtSrRXy99v55CFX vZk43IJuf1X9d6CQLl075CFuu5/Oys6EwYSawzk0iZamSVUjy9LANvOHsSKUag4l5ZR9nR Q3HlMi8k3dy1cxqrx9MNhyByLxphQeKZcd+bAxaElUyTvpVkQJS4oaIFSPIPWBwG7gb0HL AChWt/fe3Tma07iCZKUYsldPKXecOY2zpmpzjEFW0m1Ll51NyD0YY7gKE/Zb1A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1686427785; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=VN3pKad915lgXyIEKLmAqU9HFdxhV2U8JR5HtaJJWAo=; b=qeRl1VvSqXcJA/dkR81UjTvbzFNl35KrBMfEEJ9dLP6GgKhRJYWyergbo9UAvaIL3/t4PF efaD08GmnCbVq0CA== To: Michael Ellerman , linux-kernel@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-arch@vger.kernel.org, ldufour@linux.ibm.com, bp@alien8.de, dave.hansen@linux.intel.com, mingo@redhat.com, x86@kernel.org Subject: Re: [PATCH 6/9] cpu/SMT: Allow enabling partial SMT states via sysfs In-Reply-To: <20230524155630.794584-6-mpe@ellerman.id.au> References: <20230524155630.794584-1-mpe@ellerman.id.au> <20230524155630.794584-6-mpe@ellerman.id.au> Date: Sat, 10 Jun 2023 22:09:44 +0200 Message-ID: <87r0qj84fr.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Thu, May 25 2023 at 01:56, Michael Ellerman wrote: > There is a hook which allows arch code to control how many threads per Can you please write out architecture in changelogs and comments? I know 'arch' is commonly used but while my brain parser tolerates 'arch_' prefixes it raises an exception on 'arch' in prose as 'arch' is a regular word with a completely different meaning. Changelogs and comments are not space constraint. > @@ -2505,20 +2505,38 @@ __store_smt_control(struct device *dev, struct device_attribute *attr, > if (cpu_smt_control == CPU_SMT_NOT_SUPPORTED) > return -ENODEV; > > - if (sysfs_streq(buf, "on")) > + if (sysfs_streq(buf, "on")) { > ctrlval = CPU_SMT_ENABLED; > - else if (sysfs_streq(buf, "off")) > + num_threads = cpu_smt_max_threads; > + } else if (sysfs_streq(buf, "off")) { > ctrlval = CPU_SMT_DISABLED; > - else if (sysfs_streq(buf, "forceoff")) > + num_threads = 1; > + } else if (sysfs_streq(buf, "forceoff")) { > ctrlval = CPU_SMT_FORCE_DISABLED; > - else > + num_threads = 1; > + } else if (kstrtoint(buf, 10, &num_threads) == 0) { > + if (num_threads == 1) > + ctrlval = CPU_SMT_DISABLED; > + else if (num_threads > 1 && topology_smt_threads_supported(num_threads)) > + ctrlval = CPU_SMT_ENABLED; > + else > + return -EINVAL; > + } else { > return -EINVAL; > + } > > ret = lock_device_hotplug_sysfs(); > if (ret) > return ret; > > - if (ctrlval != cpu_smt_control) { > + orig_threads = cpu_smt_num_threads; > + cpu_smt_num_threads = num_threads; > + > + if (num_threads > orig_threads) { > + ret = cpuhp_smt_enable(); > + } else if (num_threads < orig_threads) { > + ret = cpuhp_smt_disable(ctrlval); > + } else if (ctrlval != cpu_smt_control) { > switch (ctrlval) { > case CPU_SMT_ENABLED: > ret = cpuhp_smt_enable(); This switch case does not make sense anymore. The only situation which reaches this is when the control value goes from CPU_SMT_DISABLED to CPU_SMT_FORCE_DISABLED because that's not changing the number of threads. So something like this is completely sufficient: if (num_threads > orig_threads) ret = cpuhp_smt_enable(); else if (num_threads < orig_threads || ctrval == CPU_SMT_FORCE_DISABLED) ret = cpuhp_smt_disable(ctrlval); No? Thanks, tglx From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95A82C7EE29 for ; Sat, 10 Jun 2023 20:18:07 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4Qdq5B03fDz3dyN for ; Sun, 11 Jun 2023 06:18:06 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=linutronix.de header.i=@linutronix.de header.a=rsa-sha256 header.s=2020 header.b=ZJPuUMqP; dkim=fail reason="signature verification failed" header.d=linutronix.de header.i=@linutronix.de header.a=ed25519-sha256 header.s=2020e header.b=qeRl1VvS; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linutronix.de (client-ip=193.142.43.55; helo=galois.linutronix.de; envelope-from=tglx@linutronix.de; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=linutronix.de header.i=@linutronix.de header.a=rsa-sha256 header.s=2020 header.b=ZJPuUMqP; dkim=pass header.d=linutronix.de header.i=@linutronix.de header.a=ed25519-sha256 header.s=2020e header.b=qeRl1VvS; dkim-atps=neutral Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Qdq4G116Fz3cLX for ; Sun, 11 Jun 2023 06:17:18 +1000 (AEST) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1686427785; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=VN3pKad915lgXyIEKLmAqU9HFdxhV2U8JR5HtaJJWAo=; b=ZJPuUMqPysjPBQOtwRD8hr8P3yWoBfFxIFRfQbmUhqrHISkVZgbVnK1l0yUcMF13n0ef88 A2mJqnviZJYpqgkQxY2B/Iddyx7txFX0h7NoqsWvq/aS5ZDorHIECmwNtSrRXy99v55CFX vZk43IJuf1X9d6CQLl075CFuu5/Oys6EwYSawzk0iZamSVUjy9LANvOHsSKUag4l5ZR9nR Q3HlMi8k3dy1cxqrx9MNhyByLxphQeKZcd+bAxaElUyTvpVkQJS4oaIFSPIPWBwG7gb0HL AChWt/fe3Tma07iCZKUYsldPKXecOY2zpmpzjEFW0m1Ll51NyD0YY7gKE/Zb1A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1686427785; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=VN3pKad915lgXyIEKLmAqU9HFdxhV2U8JR5HtaJJWAo=; b=qeRl1VvSqXcJA/dkR81UjTvbzFNl35KrBMfEEJ9dLP6GgKhRJYWyergbo9UAvaIL3/t4PF efaD08GmnCbVq0CA== To: Michael Ellerman , linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/9] cpu/SMT: Allow enabling partial SMT states via sysfs In-Reply-To: <20230524155630.794584-6-mpe@ellerman.id.au> References: <20230524155630.794584-1-mpe@ellerman.id.au> <20230524155630.794584-6-mpe@ellerman.id.au> Date: Sat, 10 Jun 2023 22:09:44 +0200 Message-ID: <87r0qj84fr.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, x86@kernel.org, dave.hansen@linux.intel.com, mingo@redhat.com, bp@alien8.de, ldufour@linux.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, May 25 2023 at 01:56, Michael Ellerman wrote: > There is a hook which allows arch code to control how many threads per Can you please write out architecture in changelogs and comments? I know 'arch' is commonly used but while my brain parser tolerates 'arch_' prefixes it raises an exception on 'arch' in prose as 'arch' is a regular word with a completely different meaning. Changelogs and comments are not space constraint. > @@ -2505,20 +2505,38 @@ __store_smt_control(struct device *dev, struct device_attribute *attr, > if (cpu_smt_control == CPU_SMT_NOT_SUPPORTED) > return -ENODEV; > > - if (sysfs_streq(buf, "on")) > + if (sysfs_streq(buf, "on")) { > ctrlval = CPU_SMT_ENABLED; > - else if (sysfs_streq(buf, "off")) > + num_threads = cpu_smt_max_threads; > + } else if (sysfs_streq(buf, "off")) { > ctrlval = CPU_SMT_DISABLED; > - else if (sysfs_streq(buf, "forceoff")) > + num_threads = 1; > + } else if (sysfs_streq(buf, "forceoff")) { > ctrlval = CPU_SMT_FORCE_DISABLED; > - else > + num_threads = 1; > + } else if (kstrtoint(buf, 10, &num_threads) == 0) { > + if (num_threads == 1) > + ctrlval = CPU_SMT_DISABLED; > + else if (num_threads > 1 && topology_smt_threads_supported(num_threads)) > + ctrlval = CPU_SMT_ENABLED; > + else > + return -EINVAL; > + } else { > return -EINVAL; > + } > > ret = lock_device_hotplug_sysfs(); > if (ret) > return ret; > > - if (ctrlval != cpu_smt_control) { > + orig_threads = cpu_smt_num_threads; > + cpu_smt_num_threads = num_threads; > + > + if (num_threads > orig_threads) { > + ret = cpuhp_smt_enable(); > + } else if (num_threads < orig_threads) { > + ret = cpuhp_smt_disable(ctrlval); > + } else if (ctrlval != cpu_smt_control) { > switch (ctrlval) { > case CPU_SMT_ENABLED: > ret = cpuhp_smt_enable(); This switch case does not make sense anymore. The only situation which reaches this is when the control value goes from CPU_SMT_DISABLED to CPU_SMT_FORCE_DISABLED because that's not changing the number of threads. So something like this is completely sufficient: if (num_threads > orig_threads) ret = cpuhp_smt_enable(); else if (num_threads < orig_threads || ctrval == CPU_SMT_FORCE_DISABLED) ret = cpuhp_smt_disable(ctrlval); No? Thanks, tglx