From: Takashi Iwai <tiwai@suse.de>
To: Yanteng Si <siyanteng@loongson.cn>
Cc: tiwai@suse.com, perex@perex.cz, chenhuacai@loongson.cn,
alsa-devel@alsa-project.org, loongarch@lists.linux.dev,
loongson-kernel@lists.loongnix.cn,
Yingkun Meng <mengyingkun@loongson.cn>
Subject: Re: [PATCH 3/4] ALSA: hda: Workaround for SDnCTL register on loongson controller
Date: Mon, 05 Jun 2023 09:36:27 +0200 [thread overview]
Message-ID: <87r0qqicn8.wl-tiwai@suse.de> (raw)
In-Reply-To: <74a63661726b8c44be72bf3bd35a3259f2ae2e6a.1685501806.git.siyanteng@loongson.cn>
On Wed, 31 May 2023 05:21:33 +0200,
Yanteng Si wrote:
>
> On loongson controller, after calling snd_hdac_stream_updateb()
> to enable DMA engine, the SDnCTL.STRM will become to zero. We
> need to access SDnCTL in dword to keep SDnCTL.STRM is not changed.
>
> Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
> Signed-off-by: Yingkun Meng <mengyingkun@loongson.cn>
> ---
> sound/hda/hdac_stream.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c
> index 1f56fd33b9af..90fbf9fea2b3 100644
> --- a/sound/hda/hdac_stream.c
> +++ b/sound/hda/hdac_stream.c
> @@ -13,6 +13,7 @@
> #include <sound/hdaudio.h>
> #include <sound/hda_register.h>
> #include "trace.h"
> +#include "../pci/hda/hda_controller.h"
>
> /*
> * the hdac_stream library is intended to be used with the following
> @@ -130,6 +131,7 @@ EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
> void snd_hdac_stream_start(struct hdac_stream *azx_dev)
> {
> struct hdac_bus *bus = azx_dev->bus;
> + struct azx *chip = bus_to_azx(bus);
> int stripe_ctl;
>
> trace_snd_hdac_stream_start(bus, azx_dev);
> @@ -150,7 +152,11 @@ void snd_hdac_stream_start(struct hdac_stream *azx_dev)
> stripe_ctl);
> }
> /* set DMA start and interrupt mask */
> - snd_hdac_stream_updateb(azx_dev, SD_CTL,
> + if (chip->driver_caps & AZX_DCAPS_LOONGSON_WORKAROUND)
> + snd_hdac_stream_updatel(azx_dev, SD_CTL,
> + 0, SD_CTL_DMA_START | SD_INT_MASK);
> + else
> + snd_hdac_stream_updateb(azx_dev, SD_CTL,
> 0, SD_CTL_DMA_START | SD_INT_MASK);
Similarly like the patch 2, this has to be handled with a new flag
added to struct hdac_bus.
Takashi
next prev parent reply other threads:[~2023-06-05 7:37 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-31 3:21 [PATCH 0/4] Add Loongson HD Audio support Yanteng Si
2023-05-31 3:21 ` [PATCH 1/4] ALSA: hda: Add Loongson LS7A HD-Audio support Yanteng Si
2023-05-31 3:21 ` [PATCH 2/4] ALSA: hda: Using polling mode for loongson controller by default Yanteng Si
2023-06-05 7:35 ` Takashi Iwai
2023-06-06 12:10 ` Yanteng Si
2023-05-31 3:21 ` [PATCH 3/4] ALSA: hda: Workaround for SDnCTL register on loongson controller Yanteng Si
2023-06-05 7:36 ` Takashi Iwai [this message]
2023-06-06 12:14 ` Yanteng Si
2023-05-31 3:21 ` [PATCH 4/4] ALSA: hda/intel: Workaround for WALLCLK register for " Yanteng Si
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