[igt-dev] [PATCH i-g-t 00/15] PMU: multi-tile support

[igt-dev] [PATCH i-g-t 00/15] PMU: multi-tile support

[Umesh Nerlige Ramappa]

From: root <root@DUT4385MTLH.fm.intel.com>

Enable IGT PMU support for multi-tile platforms.
Add multi-tile support for intel_gpu_top.

v2: (Tvrtko)
- Instead of adding gtN suffix to item, add it to parent group
- Show split gt values only if -p option is specified
- Display aggregate value as default without -p option
- Break down patches into reviewable units

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Riana Tauro (1):
  perf_pmu: Use correct pmu config for multi-tile

Tvrtko Ursulin (3):
  perf_pmu: Support multi-tile in rc6 subtest
  perf_pmu: Two new rc6 subtests
  perf_pmu: Support multi-tile in frequency subtest

Umesh Nerlige Ramappa (11):
  perf_pmu: Quiesce GPU if measuring idle busyness without spinner
  intel_gpu_top: Add an array of freq and rc6 counters
  intel_gpu_top: Determine number of tiles
  intel_gpu_top: Capture freq and rc6 counters from each gt
  intel_gpu_top: Switch pmu_counter to use aggregated values
  intel_gpu_top: Add definitions for gt-specific items and groups
  intel_gpu_top: Bump up size of groups to accomodate multi-gt
  intel_gpu_top: Increase visibility for class_view
  intel_gpu_top: Show gt specific values if requested
  intel_gpu_top: Reduce one level of indent
  intel_gpu_top: Add gt specific values to header in interactive mode

 include/drm-uapi/i915_drm.h |  17 +-
 tests/i915/perf_pmu.c       | 381 +++++++++++++++++++++++++++---------
 tools/intel_gpu_top.c       | 238 ++++++++++++++++++----
 3 files changed, 507 insertions(+), 129 deletions(-)

-- 
2.34.1

[igt-dev] [PATCH i-g-t 01/15] perf_pmu: Support multi-tile in rc6 subtest

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Teach test how to wake up a particular tile and make it iterate all of
them using dynamic subtests.

v2: Finalize SHIFT to 60. Drop FIXME from i915_drm.h

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 include/drm-uapi/i915_drm.h | 17 ++++++++++++++-
 tests/i915/perf_pmu.c       | 41 ++++++++++++++++++++++++++-----------
 2 files changed, 45 insertions(+), 13 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index a0876ee41..e164ad014 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -280,7 +280,16 @@ enum drm_i915_pmu_engine_sample {
 #define I915_PMU_ENGINE_SEMA(class, instance) \
 	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
 
-#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
+/*
+ * Top 4 bits of every non-engine counter are GT id.
+ */
+#define __I915_PMU_GT_SHIFT (60)
+
+#define ___I915_PMU_OTHER(gt, x) \
+	(((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \
+	((__u64)(gt) << __I915_PMU_GT_SHIFT))
+
+#define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x)
 
 #define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)
 #define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)
@@ -290,6 +299,12 @@ enum drm_i915_pmu_engine_sample {
 
 #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
 
+#define __I915_PMU_ACTUAL_FREQUENCY(gt)		___I915_PMU_OTHER(gt, 0)
+#define __I915_PMU_REQUESTED_FREQUENCY(gt)	___I915_PMU_OTHER(gt, 1)
+#define __I915_PMU_INTERRUPTS(gt)		___I915_PMU_OTHER(gt, 2)
+#define __I915_PMU_RC6_RESIDENCY(gt)		___I915_PMU_OTHER(gt, 3)
+#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt)	___I915_PMU_OTHER(gt, 4)
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index c5f083bbd..97ad09d76 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -1707,8 +1707,16 @@ static bool wait_for_suspended(int gem_fd)
 	return suspended;
 }
 
+static int open_forcewake_handle(int fd, unsigned int gt)
+{
+	if (getenv("IGT_NO_FORCEWAKE"))
+		return -1;
+
+	return igt_debugfs_gt_open(fd, gt, "forcewake_user", O_WRONLY);
+}
+
 static void
-test_rc6(int gem_fd, unsigned int flags)
+test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
 {
 	int64_t duration_ns = 2e9;
 	uint64_t idle, busy, prev, ts[2];
@@ -1717,7 +1725,7 @@ test_rc6(int gem_fd, unsigned int flags)
 
 	gem_quiescent_gpu(gem_fd);
 
-	fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
+	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
 
 	if (flags & TEST_RUNTIME_PM) {
 		drmModeRes *res;
@@ -1784,8 +1792,8 @@ test_rc6(int gem_fd, unsigned int flags)
 	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
 
 	/* Wake up device and check no RC6. */
-	fw = igt_open_forcewake_handle(gem_fd);
-	igt_assert(fw >= 0);
+	fw = open_forcewake_handle(gem_fd, gt);
+	igt_require(fw >= 0);
 	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
 
 	prev = pmu_read_single(fd);
@@ -2174,12 +2182,17 @@ static void pmu_read(int i915)
 		for_each_if((e)->class == I915_ENGINE_CLASS_RENDER) \
 			igt_dynamic_f("%s", e->name)
 
+#define for_each_gt(i915, gtid, tmp) \
+	for ((gtid) = 0; \
+	     ((tmp) = igt_sysfs_gt_open((i915), (gtid))) != -1; \
+	     close(tmp), (gtid)++)
+
 igt_main
 {
 	const struct intel_execution_engine2 *e;
 	unsigned int num_engines = 0;
 	const intel_ctx_t *ctx = NULL;
-	int fd = -1;
+	int gt, tmp, fd = -1;
 
 	/**
 	 * All PMU should be accompanied by a test.
@@ -2396,17 +2409,21 @@ igt_main
 	/**
 	 * Test RC6 residency reporting.
 	 */
-	igt_subtest("rc6")
-		test_rc6(fd, 0);
+	igt_subtest_with_dynamic("rc6") {
+		for_each_gt(fd, gt, tmp) {
+			igt_dynamic_f("gt%u", gt)
+				test_rc6(fd, gt, 0);
 
-	igt_subtest("rc6-runtime-pm")
-		test_rc6(fd, TEST_RUNTIME_PM);
+			igt_dynamic_f("runtime-pm-gt%u", gt)
+				test_rc6(fd, gt, TEST_RUNTIME_PM);
 
-	igt_subtest("rc6-runtime-pm-long")
-		test_rc6(fd, TEST_RUNTIME_PM | FLAG_LONG);
+			igt_dynamic_f("runtime-pm-long-gt%u", gt)
+				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
+		}
+	}
 
 	igt_subtest("rc6-suspend")
-		test_rc6(fd, TEST_S3);
+		test_rc6(fd, 0, TEST_S3);
 
 	/**
 	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 01/15] perf_pmu: Support multi-tile in rc6 subtest

[Dixit, Ashutosh]

On Fri, 05 May 2023 17:55:14 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh/Tvrtko,

> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Teach test how to wake up a particular tile and make it iterate all of
> them using dynamic subtests.
>
> v2: Finalize SHIFT to 60. Drop FIXME from i915_drm.h
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  include/drm-uapi/i915_drm.h | 17 ++++++++++++++-
>  tests/i915/perf_pmu.c       | 41 ++++++++++++++++++++++++++-----------
>  2 files changed, 45 insertions(+), 13 deletions(-)
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index a0876ee41..e164ad014 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -280,7 +280,16 @@ enum drm_i915_pmu_engine_sample {
>  #define I915_PMU_ENGINE_SEMA(class, instance) \
>	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
>
> -#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
> +/*
> + * Top 4 bits of every non-engine counter are GT id.
> + */
> +#define __I915_PMU_GT_SHIFT (60)
> +
> +#define ___I915_PMU_OTHER(gt, x) \
> +	(((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \
> +	((__u64)(gt) << __I915_PMU_GT_SHIFT))
> +
> +#define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x)

Typically we don't modify include/drm-uapi/i915_drm.h directly, it is
sync'd with the kernel.

So maybe let's add the above to lib/i915/i915_drm_local.h.

>
>  #define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)
>  #define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)
> @@ -290,6 +299,12 @@ enum drm_i915_pmu_engine_sample {
>
>  #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
>
> +#define __I915_PMU_ACTUAL_FREQUENCY(gt)		___I915_PMU_OTHER(gt, 0)
> +#define __I915_PMU_REQUESTED_FREQUENCY(gt)	___I915_PMU_OTHER(gt, 1)
> +#define __I915_PMU_INTERRUPTS(gt)		___I915_PMU_OTHER(gt, 2)
> +#define __I915_PMU_RC6_RESIDENCY(gt)		___I915_PMU_OTHER(gt, 3)
> +#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt)	___I915_PMU_OTHER(gt, 4)
> +
>  /* Each region is a minimum of 16k, and there are at most 255 of them.
>   */
>  #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> index c5f083bbd..97ad09d76 100644
> --- a/tests/i915/perf_pmu.c
> +++ b/tests/i915/perf_pmu.c
> @@ -1707,8 +1707,16 @@ static bool wait_for_suspended(int gem_fd)
>	return suspended;
>  }
>
> +static int open_forcewake_handle(int fd, unsigned int gt)
> +{
> +	if (getenv("IGT_NO_FORCEWAKE"))
> +		return -1;
> +
> +	return igt_debugfs_gt_open(fd, gt, "forcewake_user", O_WRONLY);
> +}

Let's create a new function igt_open_forcewake_gt_handle() below
igt_open_forcewake_handle() in lib/igt_gt.c and add this code there so the
code can be shared.

> +
>  static void
> -test_rc6(int gem_fd, unsigned int flags)
> +test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
>  {
>	int64_t duration_ns = 2e9;
>	uint64_t idle, busy, prev, ts[2];
> @@ -1717,7 +1725,7 @@ test_rc6(int gem_fd, unsigned int flags)
>
>	gem_quiescent_gpu(gem_fd);
>
> -	fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
> +	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
>
>	if (flags & TEST_RUNTIME_PM) {
>		drmModeRes *res;
> @@ -1784,8 +1792,8 @@ test_rc6(int gem_fd, unsigned int flags)
>	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
>
>	/* Wake up device and check no RC6. */
> -	fw = igt_open_forcewake_handle(gem_fd);
> -	igt_assert(fw >= 0);
> +	fw = open_forcewake_handle(gem_fd, gt);
> +	igt_require(fw >= 0);

Why not igt_assert?

>	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
>
>	prev = pmu_read_single(fd);
> @@ -2174,12 +2182,17 @@ static void pmu_read(int i915)
>		for_each_if((e)->class == I915_ENGINE_CLASS_RENDER) \
>			igt_dynamic_f("%s", e->name)
>
> +#define for_each_gt(i915, gtid, tmp) \
> +	for ((gtid) = 0; \
> +	     ((tmp) = igt_sysfs_gt_open((i915), (gtid))) != -1; \
> +	     close(tmp), (gtid)++)

Use i915_for_each_gt from lib/ here.

Thanks.
--
Ashutosh

> +
>  igt_main
>  {
>	const struct intel_execution_engine2 *e;
>	unsigned int num_engines = 0;
>	const intel_ctx_t *ctx = NULL;
> -	int fd = -1;
> +	int gt, tmp, fd = -1;
>
>	/**
>	 * All PMU should be accompanied by a test.
> @@ -2396,17 +2409,21 @@ igt_main
>	/**
>	 * Test RC6 residency reporting.
>	 */
> -	igt_subtest("rc6")
> -		test_rc6(fd, 0);
> +	igt_subtest_with_dynamic("rc6") {
> +		for_each_gt(fd, gt, tmp) {
> +			igt_dynamic_f("gt%u", gt)
> +				test_rc6(fd, gt, 0);
>
> -	igt_subtest("rc6-runtime-pm")
> -		test_rc6(fd, TEST_RUNTIME_PM);
> +			igt_dynamic_f("runtime-pm-gt%u", gt)
> +				test_rc6(fd, gt, TEST_RUNTIME_PM);
>
> -	igt_subtest("rc6-runtime-pm-long")
> -		test_rc6(fd, TEST_RUNTIME_PM | FLAG_LONG);
> +			igt_dynamic_f("runtime-pm-long-gt%u", gt)
> +				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
> +		}
> +	}
>
>	igt_subtest("rc6-suspend")
> -		test_rc6(fd, TEST_S3);
> +		test_rc6(fd, 0, TEST_S3);
>
>	/**
>	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
> --
> 2.34.1
>

Re: [igt-dev] [PATCH i-g-t 01/15] perf_pmu: Support multi-tile in rc6 subtest

[Tvrtko Ursulin]

On 12/05/2023 03:28, Dixit, Ashutosh wrote:
> On Fri, 05 May 2023 17:55:14 -0700, Umesh Nerlige Ramappa wrote:
>>
> 
> Hi Umesh/Tvrtko,
> 
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Teach test how to wake up a particular tile and make it iterate all of
>> them using dynamic subtests.
>>
>> v2: Finalize SHIFT to 60. Drop FIXME from i915_drm.h
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>>   include/drm-uapi/i915_drm.h | 17 ++++++++++++++-
>>   tests/i915/perf_pmu.c       | 41 ++++++++++++++++++++++++++-----------
>>   2 files changed, 45 insertions(+), 13 deletions(-)
>>
>> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
>> index a0876ee41..e164ad014 100644
>> --- a/include/drm-uapi/i915_drm.h
>> +++ b/include/drm-uapi/i915_drm.h
>> @@ -280,7 +280,16 @@ enum drm_i915_pmu_engine_sample {
>>   #define I915_PMU_ENGINE_SEMA(class, instance) \
>> 	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
>>
>> -#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
>> +/*
>> + * Top 4 bits of every non-engine counter are GT id.
>> + */
>> +#define __I915_PMU_GT_SHIFT (60)
>> +
>> +#define ___I915_PMU_OTHER(gt, x) \
>> +	(((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \
>> +	((__u64)(gt) << __I915_PMU_GT_SHIFT))
>> +
>> +#define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x)
> 
> Typically we don't modify include/drm-uapi/i915_drm.h directly, it is
> sync'd with the kernel.
> 
> So maybe let's add the above to lib/i915/i915_drm_local.h.
> 
>>
>>   #define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)
>>   #define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)
>> @@ -290,6 +299,12 @@ enum drm_i915_pmu_engine_sample {
>>
>>   #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
>>
>> +#define __I915_PMU_ACTUAL_FREQUENCY(gt)		___I915_PMU_OTHER(gt, 0)
>> +#define __I915_PMU_REQUESTED_FREQUENCY(gt)	___I915_PMU_OTHER(gt, 1)
>> +#define __I915_PMU_INTERRUPTS(gt)		___I915_PMU_OTHER(gt, 2)
>> +#define __I915_PMU_RC6_RESIDENCY(gt)		___I915_PMU_OTHER(gt, 3)
>> +#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt)	___I915_PMU_OTHER(gt, 4)
>> +
>>   /* Each region is a minimum of 16k, and there are at most 255 of them.
>>    */
>>   #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
>> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
>> index c5f083bbd..97ad09d76 100644
>> --- a/tests/i915/perf_pmu.c
>> +++ b/tests/i915/perf_pmu.c
>> @@ -1707,8 +1707,16 @@ static bool wait_for_suspended(int gem_fd)
>> 	return suspended;
>>   }
>>
>> +static int open_forcewake_handle(int fd, unsigned int gt)
>> +{
>> +	if (getenv("IGT_NO_FORCEWAKE"))
>> +		return -1;
>> +
>> +	return igt_debugfs_gt_open(fd, gt, "forcewake_user", O_WRONLY);
>> +}
> 
> Let's create a new function igt_open_forcewake_gt_handle() below
> igt_open_forcewake_handle() in lib/igt_gt.c and add this code there so the
> code can be shared.

Typically we'd move to lib/ only when there are 2-3 callers and so it is 
clear helper is useful. Don't know, I am okay either way.

>> +
>>   static void
>> -test_rc6(int gem_fd, unsigned int flags)
>> +test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
>>   {
>> 	int64_t duration_ns = 2e9;
>> 	uint64_t idle, busy, prev, ts[2];
>> @@ -1717,7 +1725,7 @@ test_rc6(int gem_fd, unsigned int flags)
>>
>> 	gem_quiescent_gpu(gem_fd);
>>
>> -	fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
>> +	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
>>
>> 	if (flags & TEST_RUNTIME_PM) {
>> 		drmModeRes *res;
>> @@ -1784,8 +1792,8 @@ test_rc6(int gem_fd, unsigned int flags)
>> 	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
>>
>> 	/* Wake up device and check no RC6. */
>> -	fw = igt_open_forcewake_handle(gem_fd);
>> -	igt_assert(fw >= 0);
>> +	fw = open_forcewake_handle(gem_fd, gt);
>> +	igt_require(fw >= 0);
> 
> Why not igt_assert?

It probably was to support running the test on old kernels. Although I 
am not sure if recently we have been disciplined enough with this 
requirement.

>> 	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
>>
>> 	prev = pmu_read_single(fd);
>> @@ -2174,12 +2182,17 @@ static void pmu_read(int i915)
>> 		for_each_if((e)->class == I915_ENGINE_CLASS_RENDER) \
>> 			igt_dynamic_f("%s", e->name)
>>
>> +#define for_each_gt(i915, gtid, tmp) \
>> +	for ((gtid) = 0; \
>> +	     ((tmp) = igt_sysfs_gt_open((i915), (gtid))) != -1; \
>> +	     close(tmp), (gtid)++)
> 
> Use i915_for_each_gt from lib/ here.

Yeah I guess these patches predate much of the IGT code added for 
supporting multi-tile in the upstream since. Shrug.

Regards,

Tvrtko

> 
> Thanks.
> --
> Ashutosh
> 
>> +
>>   igt_main
>>   {
>> 	const struct intel_execution_engine2 *e;
>> 	unsigned int num_engines = 0;
>> 	const intel_ctx_t *ctx = NULL;
>> -	int fd = -1;
>> +	int gt, tmp, fd = -1;
>>
>> 	/**
>> 	 * All PMU should be accompanied by a test.
>> @@ -2396,17 +2409,21 @@ igt_main
>> 	/**
>> 	 * Test RC6 residency reporting.
>> 	 */
>> -	igt_subtest("rc6")
>> -		test_rc6(fd, 0);
>> +	igt_subtest_with_dynamic("rc6") {
>> +		for_each_gt(fd, gt, tmp) {
>> +			igt_dynamic_f("gt%u", gt)
>> +				test_rc6(fd, gt, 0);
>>
>> -	igt_subtest("rc6-runtime-pm")
>> -		test_rc6(fd, TEST_RUNTIME_PM);
>> +			igt_dynamic_f("runtime-pm-gt%u", gt)
>> +				test_rc6(fd, gt, TEST_RUNTIME_PM);
>>
>> -	igt_subtest("rc6-runtime-pm-long")
>> -		test_rc6(fd, TEST_RUNTIME_PM | FLAG_LONG);
>> +			igt_dynamic_f("runtime-pm-long-gt%u", gt)
>> +				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
>> +		}
>> +	}
>>
>> 	igt_subtest("rc6-suspend")
>> -		test_rc6(fd, TEST_S3);
>> +		test_rc6(fd, 0, TEST_S3);
>>
>> 	/**
>> 	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
>> --
>> 2.34.1
>>

Re: [igt-dev] [PATCH i-g-t 01/15] perf_pmu: Support multi-tile in rc6 subtest

[Umesh Nerlige Ramappa]

On Fri, May 12, 2023 at 01:14:37PM +0100, Tvrtko Ursulin wrote:
>
>On 12/05/2023 03:28, Dixit, Ashutosh wrote:
>>On Fri, 05 May 2023 17:55:14 -0700, Umesh Nerlige Ramappa wrote:
>>>
>>
>>Hi Umesh/Tvrtko,
>>
>>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>>Teach test how to wake up a particular tile and make it iterate all of
>>>them using dynamic subtests.
>>>
>>>v2: Finalize SHIFT to 60. Drop FIXME from i915_drm.h
>>>
>>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>---
>>>  include/drm-uapi/i915_drm.h | 17 ++++++++++++++-
>>>  tests/i915/perf_pmu.c       | 41 ++++++++++++++++++++++++++-----------
>>>  2 files changed, 45 insertions(+), 13 deletions(-)
>>>
>>>diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
>>>index a0876ee41..e164ad014 100644
>>>--- a/include/drm-uapi/i915_drm.h
>>>+++ b/include/drm-uapi/i915_drm.h
>>>@@ -280,7 +280,16 @@ enum drm_i915_pmu_engine_sample {
>>>  #define I915_PMU_ENGINE_SEMA(class, instance) \
>>>	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
>>>
>>>-#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
>>>+/*
>>>+ * Top 4 bits of every non-engine counter are GT id.
>>>+ */
>>>+#define __I915_PMU_GT_SHIFT (60)
>>>+
>>>+#define ___I915_PMU_OTHER(gt, x) \
>>>+	(((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \
>>>+	((__u64)(gt) << __I915_PMU_GT_SHIFT))
>>>+
>>>+#define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x)
>>
>>Typically we don't modify include/drm-uapi/i915_drm.h directly, it is
>>sync'd with the kernel.
>>
>>So maybe let's add the above to lib/i915/i915_drm_local.h.

sure

>>
>>>
>>>  #define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)
>>>  #define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)
>>>@@ -290,6 +299,12 @@ enum drm_i915_pmu_engine_sample {
>>>
>>>  #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
>>>
>>>+#define __I915_PMU_ACTUAL_FREQUENCY(gt)		___I915_PMU_OTHER(gt, 0)
>>>+#define __I915_PMU_REQUESTED_FREQUENCY(gt)	___I915_PMU_OTHER(gt, 1)
>>>+#define __I915_PMU_INTERRUPTS(gt)		___I915_PMU_OTHER(gt, 2)
>>>+#define __I915_PMU_RC6_RESIDENCY(gt)		___I915_PMU_OTHER(gt, 3)
>>>+#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt)	___I915_PMU_OTHER(gt, 4)
>>>+
>>>  /* Each region is a minimum of 16k, and there are at most 255 of them.
>>>   */
>>>  #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
>>>diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
>>>index c5f083bbd..97ad09d76 100644
>>>--- a/tests/i915/perf_pmu.c
>>>+++ b/tests/i915/perf_pmu.c
>>>@@ -1707,8 +1707,16 @@ static bool wait_for_suspended(int gem_fd)
>>>	return suspended;
>>>  }
>>>
>>>+static int open_forcewake_handle(int fd, unsigned int gt)
>>>+{
>>>+	if (getenv("IGT_NO_FORCEWAKE"))
>>>+		return -1;
>>>+
>>>+	return igt_debugfs_gt_open(fd, gt, "forcewake_user", O_WRONLY);
>>>+}
>>
>>Let's create a new function igt_open_forcewake_gt_handle() below
>>igt_open_forcewake_handle() in lib/igt_gt.c and add this code there so the
>>code can be shared.
>
>Typically we'd move to lib/ only when there are 2-3 callers and so it 
>is clear helper is useful. Don't know, I am okay either way.
>

leaving as is

>>>+
>>>  static void
>>>-test_rc6(int gem_fd, unsigned int flags)
>>>+test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
>>>  {
>>>	int64_t duration_ns = 2e9;
>>>	uint64_t idle, busy, prev, ts[2];
>>>@@ -1717,7 +1725,7 @@ test_rc6(int gem_fd, unsigned int flags)
>>>
>>>	gem_quiescent_gpu(gem_fd);
>>>
>>>-	fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
>>>+	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
>>>
>>>	if (flags & TEST_RUNTIME_PM) {
>>>		drmModeRes *res;
>>>@@ -1784,8 +1792,8 @@ test_rc6(int gem_fd, unsigned int flags)
>>>	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
>>>
>>>	/* Wake up device and check no RC6. */
>>>-	fw = igt_open_forcewake_handle(gem_fd);
>>>-	igt_assert(fw >= 0);
>>>+	fw = open_forcewake_handle(gem_fd, gt);
>>>+	igt_require(fw >= 0);
>>
>>Why not igt_assert?
>
>It probably was to support running the test on old kernels. Although I 
>am not sure if recently we have been disciplined enough with this 
>requirement.

If it asserted before, then maybe should assert now too. Changing to 
assert.

>
>>>	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
>>>
>>>	prev = pmu_read_single(fd);
>>>@@ -2174,12 +2182,17 @@ static void pmu_read(int i915)
>>>		for_each_if((e)->class == I915_ENGINE_CLASS_RENDER) \
>>>			igt_dynamic_f("%s", e->name)
>>>
>>>+#define for_each_gt(i915, gtid, tmp) \
>>>+	for ((gtid) = 0; \
>>>+	     ((tmp) = igt_sysfs_gt_open((i915), (gtid))) != -1; \
>>>+	     close(tmp), (gtid)++)
>>
>>Use i915_for_each_gt from lib/ here.
>
>Yeah I guess these patches predate much of the IGT code added for 
>supporting multi-tile in the upstream since. Shrug.

changing this.

Thanks,
Umesh
>
>Regards,
>
>Tvrtko
>
>>
>>Thanks.
>>--
>>Ashutosh
>>
>>>+
>>>  igt_main
>>>  {
>>>	const struct intel_execution_engine2 *e;
>>>	unsigned int num_engines = 0;
>>>	const intel_ctx_t *ctx = NULL;
>>>-	int fd = -1;
>>>+	int gt, tmp, fd = -1;
>>>
>>>	/**
>>>	 * All PMU should be accompanied by a test.
>>>@@ -2396,17 +2409,21 @@ igt_main
>>>	/**
>>>	 * Test RC6 residency reporting.
>>>	 */
>>>-	igt_subtest("rc6")
>>>-		test_rc6(fd, 0);
>>>+	igt_subtest_with_dynamic("rc6") {
>>>+		for_each_gt(fd, gt, tmp) {
>>>+			igt_dynamic_f("gt%u", gt)
>>>+				test_rc6(fd, gt, 0);
>>>
>>>-	igt_subtest("rc6-runtime-pm")
>>>-		test_rc6(fd, TEST_RUNTIME_PM);
>>>+			igt_dynamic_f("runtime-pm-gt%u", gt)
>>>+				test_rc6(fd, gt, TEST_RUNTIME_PM);
>>>
>>>-	igt_subtest("rc6-runtime-pm-long")
>>>-		test_rc6(fd, TEST_RUNTIME_PM | FLAG_LONG);
>>>+			igt_dynamic_f("runtime-pm-long-gt%u", gt)
>>>+				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
>>>+		}
>>>+	}
>>>
>>>	igt_subtest("rc6-suspend")
>>>-		test_rc6(fd, TEST_S3);
>>>+		test_rc6(fd, 0, TEST_S3);
>>>
>>>	/**
>>>	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
>>>--
>>>2.34.1
>>>

Re: [igt-dev] [PATCH i-g-t 01/15] perf_pmu: Support multi-tile in rc6 subtest

[Dixit, Ashutosh]

On Fri, 12 May 2023 17:08:24 -0700, Umesh Nerlige Ramappa wrote:
>
> On Fri, May 12, 2023 at 01:14:37PM +0100, Tvrtko Ursulin wrote:
> >
> > On 12/05/2023 03:28, Dixit, Ashutosh wrote:
> >> On Fri, 05 May 2023 17:55:14 -0700, Umesh Nerlige Ramappa wrote:
> >>> @@ -290,6 +299,12 @@ enum drm_i915_pmu_engine_sample {
> >>>
> >>>  #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
> >>>
> >>> +#define __I915_PMU_ACTUAL_FREQUENCY(gt)		___I915_PMU_OTHER(gt, 0)
> >>> +#define __I915_PMU_REQUESTED_FREQUENCY(gt)	___I915_PMU_OTHER(gt, 1)
> >>> +#define __I915_PMU_INTERRUPTS(gt)		___I915_PMU_OTHER(gt, 2)
> >>> +#define __I915_PMU_RC6_RESIDENCY(gt)		___I915_PMU_OTHER(gt, 3)
> >>> +#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt)	___I915_PMU_OTHER(gt, 4)
> >>> +
> >>>  /* Each region is a minimum of 16k, and there are at most 255 of them.
> >>>   */
> >>>  #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
> >>> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> >>> index c5f083bbd..97ad09d76 100644
> >>> --- a/tests/i915/perf_pmu.c
> >>> +++ b/tests/i915/perf_pmu.c
> >>> @@ -1707,8 +1707,16 @@ static bool wait_for_suspended(int gem_fd)
> >>>	return suspended;
> >>>  }
> >>>
> >>> +static int open_forcewake_handle(int fd, unsigned int gt)
> >>> +{
> >>> +	if (getenv("IGT_NO_FORCEWAKE"))
> >>> +		return -1;
> >>> +
> >>> +	return igt_debugfs_gt_open(fd, gt, "forcewake_user", O_WRONLY);
> >>> +}
> >>
> >> Let's create a new function igt_open_forcewake_gt_handle() below
> >> igt_open_forcewake_handle() in lib/igt_gt.c and add this code there so the
> >> code can be shared.
> >
> > Typically we'd move to lib/ only when there are 2-3 callers and so it is
> > clear helper is useful. Don't know, I am okay either way.
> >
> leaving as is

Chicken and egg. Not moving to lib/ pretty much ensures local copies will
profilerate. Hence my suggestion. Anyway.

Thanks.
--
Ashutosh

[igt-dev] [PATCH i-g-t 02/15] perf_pmu: Two new rc6 subtests

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

1.
Keep one tile awake and check rc6 counters on all tiles.

2.
Keep all tiles awake and check rc6 counters on all.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/perf_pmu.c | 149 +++++++++++++++++++++++++++++++-----------
 1 file changed, 111 insertions(+), 38 deletions(-)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 97ad09d76..8fb54aa03 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -173,6 +173,8 @@ static unsigned int measured_usleep(unsigned int usec)
 #define FLAG_LONG (16)
 #define FLAG_HANG (32)
 #define TEST_S3 (64)
+#define TEST_OTHER (128)
+#define TEST_ALL   (256)
 
 static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
 			       const struct intel_execution_engine2 *e)
@@ -1676,20 +1678,23 @@ test_frequency_idle(int gem_fd)
 		     "Actual frequency should be 0 while parked!\n");
 }
 
-static bool wait_for_rc6(int fd, int timeout)
+static bool wait_for_rc6(int fd, int timeout, unsigned int pmus, unsigned int idx)
 {
 	struct timespec tv = {};
+	uint64_t val[pmus];
 	uint64_t start, now;
 
 	/* First wait for roughly an RC6 Evaluation Interval */
 	usleep(160 * 1000);
 
 	/* Then poll for RC6 to start ticking */
-	now = pmu_read_single(fd);
+	pmu_read_multi(fd, pmus, val);
+	now = val[idx];
 	do {
 		start = now;
 		usleep(5000);
-		now = pmu_read_single(fd);
+		pmu_read_multi(fd, pmus, val);
+		now = val[idx];
 		if (now - start > 1e6)
 			return true;
 	} while (igt_seconds_elapsed(&tv) <= timeout);
@@ -1716,16 +1721,38 @@ static int open_forcewake_handle(int fd, unsigned int gt)
 }
 
 static void
-test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
+test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags)
 {
 	int64_t duration_ns = 2e9;
-	uint64_t idle, busy, prev, ts[2];
+	uint64_t idle[16], busy[16], prev[16], ts[2];
+	int fd[num_gt], fw[num_gt], gt_, pmus = 0, test_idx = -1;
 	unsigned long slept;
-	int fd, fw;
+
+	igt_require(!(flags & TEST_OTHER) ||
+		    ((flags & TEST_OTHER) && num_gt > 1));
+
+	igt_require(!(flags & TEST_ALL) ||
+		    ((flags & TEST_ALL) && num_gt > 1));
 
 	gem_quiescent_gpu(gem_fd);
 
-	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
+	fd[0] = -1;
+	for (gt_ = 0; gt_ < num_gt; gt_++) {
+		if (gt_ != gt && !(flags & TEST_OTHER))
+			continue;
+
+		if (gt_ == gt) {
+			igt_assert(test_idx == -1);
+			test_idx = pmus;
+		}
+
+		fd[pmus] = perf_i915_open_group(gem_fd,
+						__I915_PMU_RC6_RESIDENCY(gt_),
+						fd[0]);
+		igt_skip_on(fd[pmus] < 0 && errno == ENODEV);
+		pmus++;
+	}
+	igt_assert(test_idx >= 0);
 
 	if (flags & TEST_RUNTIME_PM) {
 		drmModeRes *res;
@@ -1746,21 +1773,26 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
 		 * drifted to far in advance of real RC6.
 		 */
 		if (flags & FLAG_LONG) {
-			pmu_read_single(fd);
+			pmu_read_multi(fd[0], pmus, idle);
 			sleep(5);
-			pmu_read_single(fd);
+			pmu_read_multi(fd[0], pmus, idle);
 		}
 	}
 
-	igt_require(wait_for_rc6(fd, 1));
+	igt_require(wait_for_rc6(fd[0], 1, pmus, test_idx));
 
 	/* While idle check full RC6. */
-	prev = __pmu_read_single(fd, &ts[0]);
+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
 	slept = measured_usleep(duration_ns / 1000);
-	idle = __pmu_read_single(fd, &ts[1]);
-
-	igt_debug("slept=%lu perf=%"PRIu64"\n", slept, ts[1] - ts[0]);
-	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
+	ts[1] = pmu_read_multi(fd[0], pmus, idle);
+
+	for (gt_ = 0; gt_ < pmus; gt_++) {
+		igt_debug("gt%u: idle rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
+			  gt_, idle[gt_] - prev[gt_], slept, ts[1] - ts[0]);
+		assert_within_epsilon(idle[gt_] - prev[gt_],
+				      ts[1] - ts[0],
+				      tolerance);
+	}
 
 	if (flags & TEST_S3) {
 		/*
@@ -1773,40 +1805,70 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
 		 * However, in practice it appears we are not entering rc6
 		 * immediately after resume... A bug?
 		 */
-		prev = __pmu_read_single(fd, &ts[0]);
+		ts[0] = pmu_read_multi(fd[0], pmus, prev);
 		igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
 					      SUSPEND_TEST_NONE);
-		idle = __pmu_read_single(fd, &ts[1]);
-		igt_debug("suspend=%"PRIu64", rc6=%"PRIu64"\n",
-			  ts[1] - ts[0], idle -prev);
-		//assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
+		ts[1] = pmu_read_multi(fd[0], pmus, idle);
+		for (gt_ = 0; gt_ < pmus; gt_++) {
+			igt_debug("gt%u: rc6=%"PRIu64", suspend=%"PRIu64"\n",
+				  gt_, idle[gt_] - prev[gt_], ts[1] - ts[0]);
+			// assert_within_epsilon(idle[gt_] - prev[gt_],
+			//		      ts[1] - ts[0], tolerance);
+		}
 	}
 
-	igt_assert(wait_for_rc6(fd, 5));
+	igt_assert(wait_for_rc6(fd[0], 5, pmus, test_idx));
 
-	prev = __pmu_read_single(fd, &ts[0]);
+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
 	slept = measured_usleep(duration_ns / 1000);
-	idle = __pmu_read_single(fd, &ts[1]);
-
-	igt_debug("slept=%lu perf=%"PRIu64"\n", slept, ts[1] - ts[0]);
-	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
+	ts[1] = pmu_read_multi(fd[0], pmus, idle);
+
+	for (gt_ = 0; gt_ < pmus; gt_++) {
+		igt_debug("gt%u: idle rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
+			  gt_, idle[gt_] - prev[gt_], slept, ts[1] - ts[0]);
+		assert_within_epsilon(idle[gt_] - prev[gt_],
+				      ts[1] - ts[0],
+				      tolerance);
+	}
 
 	/* Wake up device and check no RC6. */
-	fw = open_forcewake_handle(gem_fd, gt);
-	igt_require(fw >= 0);
+	for (gt_ = 0; gt_ < num_gt; gt_++) {
+		if (gt_ != gt && !(flags & TEST_ALL))
+			continue;
+
+		fw[gt_] = open_forcewake_handle(gem_fd, gt_);
+		igt_require(fw[gt_] >= 0);
+	}
+
 	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
 
-	prev = pmu_read_single(fd);
-	usleep(duration_ns / 1000);
-	busy = pmu_read_single(fd);
+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
+	slept = measured_usleep(duration_ns / 1000);
+	ts[1] = pmu_read_multi(fd[0], pmus, busy);
 
-	close(fw);
-	close(fd);
+	for (gt_ = 0; gt_ < num_gt; gt_++) {
+		if (gt_ == gt || (flags & TEST_ALL))
+			close(fw[gt_]);
+	}
+
+	for (gt_ = 0; gt_ < pmus; gt_++)
+		close(fd[gt_]);
 
 	if (flags & TEST_RUNTIME_PM)
 		igt_restore_runtime_pm();
 
-	assert_within_epsilon(busy - prev, 0.0, tolerance);
+	for (gt_ = 0; gt_ < pmus; gt_++) {
+		igt_debug("gt%u: busy rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
+			  gt_, busy[gt_] - prev[gt_], slept, ts[1] - ts[0]);
+		if (gt_ == test_idx || (flags & TEST_ALL))
+			assert_within_epsilon(busy[gt_] - prev[gt_],
+					      0.0,
+					      tolerance);
+		else
+			assert_within_epsilon(busy[gt_] - prev[gt_],
+					      ts[1] - ts[0],
+					      tolerance);
+	}
 }
 
 static void
@@ -2193,6 +2255,7 @@ igt_main
 	unsigned int num_engines = 0;
 	const intel_ctx_t *ctx = NULL;
 	int gt, tmp, fd = -1;
+	int num_gt = 0;
 
 	/**
 	 * All PMU should be accompanied by a test.
@@ -2211,6 +2274,9 @@ igt_main
 		for_each_ctx_engine(fd, ctx, e)
 			num_engines++;
 		igt_require(num_engines);
+
+		for_each_gt(fd, gt, tmp)
+			num_gt++;
 	}
 
 	igt_describe("Verify i915 pmu dir exists and read all events");
@@ -2412,18 +2478,25 @@ igt_main
 	igt_subtest_with_dynamic("rc6") {
 		for_each_gt(fd, gt, tmp) {
 			igt_dynamic_f("gt%u", gt)
-				test_rc6(fd, gt, 0);
+				test_rc6(fd, gt, num_gt, 0);
 
 			igt_dynamic_f("runtime-pm-gt%u", gt)
-				test_rc6(fd, gt, TEST_RUNTIME_PM);
+				test_rc6(fd, gt, num_gt, TEST_RUNTIME_PM);
 
 			igt_dynamic_f("runtime-pm-long-gt%u", gt)
-				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
+				test_rc6(fd, gt, num_gt,
+					 TEST_RUNTIME_PM | FLAG_LONG);
+
+			igt_dynamic_f("other-idle-gt%u", gt)
+				test_rc6(fd, gt, num_gt, TEST_OTHER);
 		}
 	}
 
 	igt_subtest("rc6-suspend")
-		test_rc6(fd, 0, TEST_S3);
+		test_rc6(fd, 0, num_gt, TEST_S3);
+
+	igt_subtest("rc6-all-gts")
+		test_rc6(fd, 0, num_gt, TEST_ALL | TEST_OTHER);
 
 	/**
 	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 02/15] perf_pmu: Two new rc6 subtests

[Umesh Nerlige Ramappa]

On Fri, May 05, 2023 at 05:55:15PM -0700, Umesh Nerlige Ramappa wrote:
>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
>1.
>Keep one tile awake and check rc6 counters on all tiles.
>
>2.
>Keep all tiles awake and check rc6 counters on all.
>
>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>---
> tests/i915/perf_pmu.c | 149 +++++++++++++++++++++++++++++++-----------
> 1 file changed, 111 insertions(+), 38 deletions(-)
>
>diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
>index 97ad09d76..8fb54aa03 100644
>--- a/tests/i915/perf_pmu.c
>+++ b/tests/i915/perf_pmu.c
>@@ -173,6 +173,8 @@ static unsigned int measured_usleep(unsigned int usec)
> #define FLAG_LONG (16)
> #define FLAG_HANG (32)
> #define TEST_S3 (64)
>+#define TEST_OTHER (128)
>+#define TEST_ALL   (256)
>
> static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> 			       const struct intel_execution_engine2 *e)
>@@ -1676,20 +1678,23 @@ test_frequency_idle(int gem_fd)
> 		     "Actual frequency should be 0 while parked!\n");
> }
>
>-static bool wait_for_rc6(int fd, int timeout)
>+static bool wait_for_rc6(int fd, int timeout, unsigned int pmus, unsigned int idx)
> {
> 	struct timespec tv = {};
>+	uint64_t val[pmus];
> 	uint64_t start, now;
>
> 	/* First wait for roughly an RC6 Evaluation Interval */
> 	usleep(160 * 1000);
>
> 	/* Then poll for RC6 to start ticking */
>-	now = pmu_read_single(fd);
>+	pmu_read_multi(fd, pmus, val);
>+	now = val[idx];
> 	do {
> 		start = now;
> 		usleep(5000);
>-		now = pmu_read_single(fd);
>+		pmu_read_multi(fd, pmus, val);
>+		now = val[idx];
> 		if (now - start > 1e6)
> 			return true;
> 	} while (igt_seconds_elapsed(&tv) <= timeout);
>@@ -1716,16 +1721,38 @@ static int open_forcewake_handle(int fd, unsigned int gt)
> }
>
> static void
>-test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
>+test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags)
> {
> 	int64_t duration_ns = 2e9;
>-	uint64_t idle, busy, prev, ts[2];
>+	uint64_t idle[16], busy[16], prev[16], ts[2];
>+	int fd[num_gt], fw[num_gt], gt_, pmus = 0, test_idx = -1;
> 	unsigned long slept;
>-	int fd, fw;
>+
>+	igt_require(!(flags & TEST_OTHER) ||
>+		    ((flags & TEST_OTHER) && num_gt > 1));
>+
>+	igt_require(!(flags & TEST_ALL) ||
>+		    ((flags & TEST_ALL) && num_gt > 1));
>
> 	gem_quiescent_gpu(gem_fd);
>
>-	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
>+	fd[0] = -1;
>+	for (gt_ = 0; gt_ < num_gt; gt_++) {
>+		if (gt_ != gt && !(flags & TEST_OTHER))
>+			continue;
>+
>+		if (gt_ == gt) {
>+			igt_assert(test_idx == -1);
>+			test_idx = pmus;
>+		}
>+
>+		fd[pmus] = perf_i915_open_group(gem_fd,
>+						__I915_PMU_RC6_RESIDENCY(gt_),
>+						fd[0]);
>+		igt_skip_on(fd[pmus] < 0 && errno == ENODEV);
>+		pmus++;
>+	}
>+	igt_assert(test_idx >= 0);
>
> 	if (flags & TEST_RUNTIME_PM) {
> 		drmModeRes *res;
>@@ -1746,21 +1773,26 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
> 		 * drifted to far in advance of real RC6.
> 		 */
> 		if (flags & FLAG_LONG) {
>-			pmu_read_single(fd);
>+			pmu_read_multi(fd[0], pmus, idle);
> 			sleep(5);
>-			pmu_read_single(fd);
>+			pmu_read_multi(fd[0], pmus, idle);
> 		}
> 	}
>
>-	igt_require(wait_for_rc6(fd, 1));
>+	igt_require(wait_for_rc6(fd[0], 1, pmus, test_idx));
>
> 	/* While idle check full RC6. */
>-	prev = __pmu_read_single(fd, &ts[0]);
>+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
> 	slept = measured_usleep(duration_ns / 1000);
>-	idle = __pmu_read_single(fd, &ts[1]);
>-
>-	igt_debug("slept=%lu perf=%"PRIu64"\n", slept, ts[1] - ts[0]);
>-	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
>+	ts[1] = pmu_read_multi(fd[0], pmus, idle);
>+
>+	for (gt_ = 0; gt_ < pmus; gt_++) {
>+		igt_debug("gt%u: idle rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
>+			  gt_, idle[gt_] - prev[gt_], slept, ts[1] - ts[0]);
>+		assert_within_epsilon(idle[gt_] - prev[gt_],
>+				      ts[1] - ts[0],
>+				      tolerance);
>+	}
>
> 	if (flags & TEST_S3) {
> 		/*
>@@ -1773,40 +1805,70 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
> 		 * However, in practice it appears we are not entering rc6
> 		 * immediately after resume... A bug?
> 		 */
>-		prev = __pmu_read_single(fd, &ts[0]);
>+		ts[0] = pmu_read_multi(fd[0], pmus, prev);
> 		igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
> 					      SUSPEND_TEST_NONE);
>-		idle = __pmu_read_single(fd, &ts[1]);
>-		igt_debug("suspend=%"PRIu64", rc6=%"PRIu64"\n",
>-			  ts[1] - ts[0], idle -prev);
>-		//assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
>+		ts[1] = pmu_read_multi(fd[0], pmus, idle);
>+		for (gt_ = 0; gt_ < pmus; gt_++) {
>+			igt_debug("gt%u: rc6=%"PRIu64", suspend=%"PRIu64"\n",
>+				  gt_, idle[gt_] - prev[gt_], ts[1] - ts[0]);
>+			// assert_within_epsilon(idle[gt_] - prev[gt_],
>+			//		      ts[1] - ts[0], tolerance);
>+		}
> 	}
>
>-	igt_assert(wait_for_rc6(fd, 5));
>+	igt_assert(wait_for_rc6(fd[0], 5, pmus, test_idx));
>
>-	prev = __pmu_read_single(fd, &ts[0]);
>+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
> 	slept = measured_usleep(duration_ns / 1000);
>-	idle = __pmu_read_single(fd, &ts[1]);
>-
>-	igt_debug("slept=%lu perf=%"PRIu64"\n", slept, ts[1] - ts[0]);
>-	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
>+	ts[1] = pmu_read_multi(fd[0], pmus, idle);
>+
>+	for (gt_ = 0; gt_ < pmus; gt_++) {
>+		igt_debug("gt%u: idle rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
>+			  gt_, idle[gt_] - prev[gt_], slept, ts[1] - ts[0]);
>+		assert_within_epsilon(idle[gt_] - prev[gt_],
>+				      ts[1] - ts[0],
>+				      tolerance);
>+	}
>
> 	/* Wake up device and check no RC6. */
>-	fw = open_forcewake_handle(gem_fd, gt);
>-	igt_require(fw >= 0);
>+	for (gt_ = 0; gt_ < num_gt; gt_++) {
>+		if (gt_ != gt && !(flags & TEST_ALL))
>+			continue;
>+
>+		fw[gt_] = open_forcewake_handle(gem_fd, gt_);
>+		igt_require(fw[gt_] >= 0);
>+	}
>+
> 	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
>
>-	prev = pmu_read_single(fd);
>-	usleep(duration_ns / 1000);
>-	busy = pmu_read_single(fd);
>+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
>+	slept = measured_usleep(duration_ns / 1000);
>+	ts[1] = pmu_read_multi(fd[0], pmus, busy);
>
>-	close(fw);
>-	close(fd);
>+	for (gt_ = 0; gt_ < num_gt; gt_++) {
>+		if (gt_ == gt || (flags & TEST_ALL))
>+			close(fw[gt_]);
>+	}
>+
>+	for (gt_ = 0; gt_ < pmus; gt_++)
>+		close(fd[gt_]);
>
> 	if (flags & TEST_RUNTIME_PM)
> 		igt_restore_runtime_pm();
>
>-	assert_within_epsilon(busy - prev, 0.0, tolerance);
>+	for (gt_ = 0; gt_ < pmus; gt_++) {
>+		igt_debug("gt%u: busy rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
>+			  gt_, busy[gt_] - prev[gt_], slept, ts[1] - ts[0]);
>+		if (gt_ == test_idx || (flags & TEST_ALL))
>+			assert_within_epsilon(busy[gt_] - prev[gt_],
>+					      0.0,
>+					      tolerance);
>+		else
>+			assert_within_epsilon(busy[gt_] - prev[gt_],
>+					      ts[1] - ts[0],
>+					      tolerance);
>+	}
> }
>
> static void
>@@ -2193,6 +2255,7 @@ igt_main
> 	unsigned int num_engines = 0;
> 	const intel_ctx_t *ctx = NULL;
> 	int gt, tmp, fd = -1;
>+	int num_gt = 0;
>
> 	/**
> 	 * All PMU should be accompanied by a test.
>@@ -2211,6 +2274,9 @@ igt_main
> 		for_each_ctx_engine(fd, ctx, e)
> 			num_engines++;
> 		igt_require(num_engines);
>+
>+		for_each_gt(fd, gt, tmp)
>+			num_gt++;
> 	}
>
> 	igt_describe("Verify i915 pmu dir exists and read all events");
>@@ -2412,18 +2478,25 @@ igt_main
> 	igt_subtest_with_dynamic("rc6") {
> 		for_each_gt(fd, gt, tmp) {
> 			igt_dynamic_f("gt%u", gt)
>-				test_rc6(fd, gt, 0);
>+				test_rc6(fd, gt, num_gt, 0);
>
> 			igt_dynamic_f("runtime-pm-gt%u", gt)
>-				test_rc6(fd, gt, TEST_RUNTIME_PM);
>+				test_rc6(fd, gt, num_gt, TEST_RUNTIME_PM);
>
> 			igt_dynamic_f("runtime-pm-long-gt%u", gt)
>-				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
>+				test_rc6(fd, gt, num_gt,
>+					 TEST_RUNTIME_PM | FLAG_LONG);
>+
>+			igt_dynamic_f("other-idle-gt%u", gt)
>+				test_rc6(fd, gt, num_gt, TEST_OTHER);
> 		}
> 	}
>
> 	igt_subtest("rc6-suspend")
>-		test_rc6(fd, 0, TEST_S3);
>+		test_rc6(fd, 0, num_gt, TEST_S3);
>+
>+	igt_subtest("rc6-all-gts")
>+		test_rc6(fd, 0, num_gt, TEST_ALL | TEST_OTHER);
>
> 	/**
> 	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
>-- 
>2.34.1
>

[igt-dev] [PATCH i-g-t 03/15] perf_pmu: Support multi-tile in frequency subtest

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Simple conversion to run the frequency tests per each tile, as dynamic
subtests, picking the correct engine to stimulate each.

v2: Added new intel_ctx_t implementation for frequency subtest.
v3: Replace distance query with mtl specific static mapping
v4: Break as soon as you find one engine in gt

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Arjun Melkaveri <arjun.melkaveri@intel.com> (v2)
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/perf_pmu.c | 197 +++++++++++++++++++++++++++++++++---------
 1 file changed, 155 insertions(+), 42 deletions(-)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 8fb54aa03..0b1177785 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -238,19 +238,6 @@ static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
 	return __spin_sync(fd, ahnd, ctx, e);
 }
 
-static igt_spin_t *spin_sync_flags(int fd, uint64_t ahnd,
-				   const intel_ctx_t *ctx, unsigned int flags)
-{
-	struct intel_execution_engine2 e = { };
-
-	e.class = gem_execbuf_flags_to_engine_class(flags);
-	e.instance = (flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK)) ==
-		     (I915_EXEC_BSD | I915_EXEC_BSD_RING2) ? 1 : 0;
-	e.flags = flags;
-
-	return spin_sync(fd, ahnd, ctx, &e);
-}
-
 static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
 {
 	if (!spin)
@@ -1539,8 +1526,127 @@ test_interrupts_sync(int gem_fd)
 	igt_assert_lte(target, busy);
 }
 
+static int
+__i915_query(int fd, struct drm_i915_query *q)
+{
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		return -errno;
+
+	return 0;
+}
+
+static int
+__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
+{
+	struct drm_i915_query q = {
+		.num_items = n_items,
+		.items_ptr = to_user_pointer(items),
+		};
+
+	return __i915_query(fd, &q);
+}
+
+#define i915_query_items(fd, items, n_items) \
+do { \
+	igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
+	errno = 0; \
+} while (0)
+
+static bool
+engine_in_gt(int i915, const struct i915_engine_class_instance *ci,
+	     unsigned int gt)
+{
+	/* If just one gt, return true always */
+	if (!IS_METEORLAKE(intel_get_drm_devid(i915)))
+		return true;
+
+	/*
+	 * This should ideally use a query mechanism, but such mechanisms are
+	 * not in upstream. Until a better solution is upstreamed, use a static
+	 * mapping here.
+	 */
+	switch (ci->engine_class) {
+		case I915_ENGINE_CLASS_RENDER:
+		case I915_ENGINE_CLASS_COMPUTE:
+		case I915_ENGINE_CLASS_COPY:
+			return gt == 0;
+		case I915_ENGINE_CLASS_VIDEO:
+		case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+			return gt == 1;
+		default:
+			igt_assert_f(0, "Unsupported engine class %d\n", ci->engine_class);
+			return false;
+	}
+}
+
+static struct i915_engine_class_instance
+find_dword_engine(int i915, const unsigned int gt)
+{
+	struct drm_i915_query_engine_info *engines;
+	struct i915_engine_class_instance ci = { -1, -1 };
+	struct drm_i915_query_item item;
+	unsigned int i;
+
+	engines = malloc(4096);
+	igt_assert(engines);
+
+	memset(engines, 0, 4096);
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	item.length = 4096;
+	item.data_ptr = to_user_pointer(engines);
+	i915_query_items(i915, &item, 1);
+	igt_assert(item.length > 0);
+
+	for (i = 0; i < engines->num_engines; i++) {
+		struct drm_i915_engine_info *e =
+			(struct drm_i915_engine_info *)&engines->engines[i];
+
+		if (!gem_class_can_store_dword(i915, e->engine.engine_class))
+			continue;
+
+		if (engine_in_gt(i915, &e->engine, gt)) {
+			ci.engine_class = e->engine.engine_class;
+			ci.engine_instance = e->engine.engine_instance;
+			break;
+		}
+	}
+
+	free(engines);
+
+	return ci;
+}
+
+static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
+				const intel_ctx_t **ctx)
+{
+	struct i915_engine_class_instance ci = { -1, -1 };
+	struct intel_execution_engine2 e = { };
+
+	ci = find_dword_engine(i915, gt);
+
+	igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
+
+	if (gem_has_contexts(i915)) {
+		e.class = ci.engine_class;
+		e.instance = ci.engine_instance;
+		e.flags = 0;
+		*ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
+	} else {
+		igt_require(gt == 0); /* Impossible anyway. */
+		e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
+		e.instance = 0;
+		e.flags = I915_EXEC_DEFAULT;
+		*ctx = intel_ctx_0(i915);
+	}
+
+	igt_debug("Using engine %u:%u\n", e.class, e.instance);
+
+	return spin_sync(i915, ahnd, *ctx, &e);
+}
+
 static void
-test_frequency(int gem_fd)
+test_frequency(int gem_fd, unsigned int gt)
 {
 	uint32_t min_freq, max_freq, boost_freq;
 	uint64_t val[2], start[2], slept;
@@ -1548,13 +1654,14 @@ test_frequency(int gem_fd)
 	igt_spin_t *spin;
 	int fd[2], sysfs;
 	uint64_t ahnd = get_reloc_ahnd(gem_fd, 0);
+	const intel_ctx_t *ctx;
 
-	sysfs = igt_sysfs_open(gem_fd);
+	sysfs = igt_sysfs_gt_open(gem_fd, gt);
 	igt_require(sysfs >= 0);
 
-	min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
-	max_freq = igt_sysfs_get_u32(sysfs, "gt_RP0_freq_mhz");
-	boost_freq = igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz");
+	min_freq = igt_sysfs_get_u32(sysfs, "rps_RPn_freq_mhz");
+	max_freq = igt_sysfs_get_u32(sysfs, "rps_RP0_freq_mhz");
+	boost_freq = igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz");
 	igt_info("Frequency: min=%u, max=%u, boost=%u MHz\n",
 		 min_freq, max_freq, boost_freq);
 	igt_require(min_freq > 0 && max_freq > 0 && boost_freq > 0);
@@ -1567,15 +1674,15 @@ test_frequency(int gem_fd)
 	/*
 	 * Set GPU to min frequency and read PMU counters.
 	 */
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == min_freq);
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", min_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == min_freq);
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", min_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == min_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") == min_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_max_freq_mhz", min_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_max_freq_mhz") == min_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_boost_freq_mhz", min_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz") == min_freq);
 
 	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
-	spin = spin_sync_flags(gem_fd, ahnd, 0, I915_EXEC_DEFAULT);
+	spin = spin_sync_gt(gem_fd, ahnd, gt, &ctx);
 
 	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
@@ -1584,6 +1691,7 @@ test_frequency(int gem_fd)
 	min[0] = 1e9*(val[0] - start[0]) / slept;
 	min[1] = 1e9*(val[1] - start[1]) / slept;
 
+	intel_ctx_destroy(gem_fd, ctx);
 	igt_spin_free(gem_fd, spin);
 	gem_quiescent_gpu(gem_fd); /* Don't leak busy bo into the next phase */
 
@@ -1592,16 +1700,16 @@ test_frequency(int gem_fd)
 	/*
 	 * Set GPU to max frequency and read PMU counters.
 	 */
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", max_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == max_freq);
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", boost_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == boost_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_max_freq_mhz", max_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_max_freq_mhz") == max_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_boost_freq_mhz", boost_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz") == boost_freq);
 
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", max_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == max_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", max_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") == max_freq);
 
 	gem_quiescent_gpu(gem_fd);
-	spin = spin_sync_flags(gem_fd, ahnd, 0, I915_EXEC_DEFAULT);
+	spin = spin_sync_gt(gem_fd, ahnd, gt, &ctx);
 
 	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
@@ -1610,16 +1718,17 @@ test_frequency(int gem_fd)
 	max[0] = 1e9*(val[0] - start[0]) / slept;
 	max[1] = 1e9*(val[1] - start[1]) / slept;
 
+	intel_ctx_destroy(gem_fd, ctx);
 	igt_spin_free(gem_fd, spin);
 	gem_quiescent_gpu(gem_fd);
 
 	/*
 	 * Restore min/max.
 	 */
-	igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq);
-	if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
+	igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq);
+	if (igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") != min_freq)
 		igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n",
-			 min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));
+			 min_freq, igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz"));
 	close(fd[0]);
 	close(fd[1]);
 	put_ahnd(ahnd);
@@ -1638,17 +1747,17 @@ test_frequency(int gem_fd)
 }
 
 static void
-test_frequency_idle(int gem_fd)
+test_frequency_idle(int gem_fd, unsigned int gt)
 {
 	uint32_t min_freq;
 	uint64_t val[2], start[2], slept;
 	double idle[2];
 	int fd[2], sysfs;
 
-	sysfs = igt_sysfs_open(gem_fd);
+	sysfs = igt_sysfs_gt_open(gem_fd, gt);
 	igt_require(sysfs >= 0);
 
-	min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
+	min_freq = igt_sysfs_get_u32(sysfs, "rps_RPn_freq_mhz");
 	close(sysfs);
 
 	/* While parked, our convention is to report the GPU at 0Hz */
@@ -2458,10 +2567,14 @@ igt_main
 	/**
 	 * Test GPU frequency.
 	 */
-	igt_subtest("frequency")
-		test_frequency(fd);
-	igt_subtest("frequency-idle")
-		test_frequency_idle(fd);
+	igt_subtest_with_dynamic("frequency") {
+		for_each_gt(fd, gt, tmp) {
+			igt_dynamic_f("gt%u", gt)
+				test_frequency(fd, gt);
+			igt_dynamic_f("idle-gt%u", gt)
+				test_frequency_idle(fd, gt);
+		}
+	}
 
 	/**
 	 * Test interrupt count reporting.
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 03/15] perf_pmu: Support multi-tile in frequency subtest

[Dixit, Ashutosh]

On Fri, 05 May 2023 17:55:16 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Hi Umesh,

> Simple conversion to run the frequency tests per each tile, as dynamic
> subtests, picking the correct engine to stimulate each.
>
> v2: Added new intel_ctx_t implementation for frequency subtest.
> v3: Replace distance query with mtl specific static mapping
> v4: Break as soon as you find one engine in gt
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Arjun Melkaveri <arjun.melkaveri@intel.com> (v2)
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/i915/perf_pmu.c | 197 +++++++++++++++++++++++++++++++++---------
>  1 file changed, 155 insertions(+), 42 deletions(-)
>
> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> index 8fb54aa03..0b1177785 100644
> --- a/tests/i915/perf_pmu.c
> +++ b/tests/i915/perf_pmu.c
> @@ -238,19 +238,6 @@ static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>	return __spin_sync(fd, ahnd, ctx, e);
>  }
>
> -static igt_spin_t *spin_sync_flags(int fd, uint64_t ahnd,
> -				   const intel_ctx_t *ctx, unsigned int flags)
> -{
> -	struct intel_execution_engine2 e = { };
> -
> -	e.class = gem_execbuf_flags_to_engine_class(flags);
> -	e.instance = (flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK)) ==
> -		     (I915_EXEC_BSD | I915_EXEC_BSD_RING2) ? 1 : 0;
> -	e.flags = flags;
> -
> -	return spin_sync(fd, ahnd, ctx, &e);
> -}
> -
>  static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>  {
>	if (!spin)
> @@ -1539,8 +1526,127 @@ test_interrupts_sync(int gem_fd)
>	igt_assert_lte(target, busy);
>  }
>
> +static int
> +__i915_query(int fd, struct drm_i915_query *q)
> +{
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> +		return -errno;
> +
> +	return 0;
> +}
> +
> +static int
> +__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
> +{
> +	struct drm_i915_query q = {
> +		.num_items = n_items,
> +		.items_ptr = to_user_pointer(items),
> +		};
> +
> +	return __i915_query(fd, &q);
> +}
> +
> +#define i915_query_items(fd, items, n_items) \
> +do { \
> +	igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
> +	errno = 0; \
> +} while (0)
> +
> +static bool
> +engine_in_gt(int i915, const struct i915_engine_class_instance *ci,
> +	     unsigned int gt)
> +{
> +	/* If just one gt, return true always */
> +	if (!IS_METEORLAKE(intel_get_drm_devid(i915)))
> +		return true;
> +
> +	/*
> +	 * This should ideally use a query mechanism, but such mechanisms are
> +	 * not in upstream. Until a better solution is upstreamed, use a static
> +	 * mapping here.
> +	 */
> +	switch (ci->engine_class) {
> +		case I915_ENGINE_CLASS_RENDER:
> +		case I915_ENGINE_CLASS_COMPUTE:
> +		case I915_ENGINE_CLASS_COPY:
> +			return gt == 0;
> +		case I915_ENGINE_CLASS_VIDEO:
> +		case I915_ENGINE_CLASS_VIDEO_ENHANCE:
> +			return gt == 1;
> +		default:
> +			igt_assert_f(0, "Unsupported engine class %d\n", ci->engine_class);
> +			return false;
> +	}
> +}

All this code is not needed, it is already there in gem_list_engines(),
which will list all engines on a gt. For usage, see intel_ctx_cfg_for_gt().

There is also intel_ctx_create_for_gt() but I think that's not needed here,
just use gem_list_engines(), as done in intel_ctx_cfg_for_gt().


> +
> +static struct i915_engine_class_instance
> +find_dword_engine(int i915, const unsigned int gt)
> +{
> +	struct drm_i915_query_engine_info *engines;
> +	struct i915_engine_class_instance ci = { -1, -1 };
> +	struct drm_i915_query_item item;
> +	unsigned int i;
> +
> +	engines = malloc(4096);
> +	igt_assert(engines);
> +
> +	memset(engines, 0, 4096);
> +	memset(&item, 0, sizeof(item));
> +	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +	item.length = 4096;
> +	item.data_ptr = to_user_pointer(engines);
> +	i915_query_items(i915, &item, 1);
> +	igt_assert(item.length > 0);
> +

So all this gets replaced by gem_list_engines().

> +	for (i = 0; i < engines->num_engines; i++) {
> +		struct drm_i915_engine_info *e =
> +			(struct drm_i915_engine_info *)&engines->engines[i];
> +
> +		if (!gem_class_can_store_dword(i915, e->engine.engine_class))
> +			continue;
> +
> +		if (engine_in_gt(i915, &e->engine, gt)) {
> +			ci.engine_class = e->engine.engine_class;
> +			ci.engine_instance = e->engine.engine_instance;
> +			break;
> +		}
> +	}

So now when we have the engines from gem_list_engines() we can just retain
tthe gem_class_can_store_dword() check in the loop above. That's all that
is needed.

> +
> +	free(engines);
> +
> +	return ci;
> +}

So from the above code we just retain need to retain find_dword_engine(),
implemented as described above.

> +
> +static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
> +				const intel_ctx_t **ctx)
> +{
> +	struct i915_engine_class_instance ci = { -1, -1 };
> +	struct intel_execution_engine2 e = { };
> +
> +	ci = find_dword_engine(i915, gt);
> +
> +	igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
> +
> +	if (gem_has_contexts(i915)) {
> +		e.class = ci.engine_class;
> +		e.instance = ci.engine_instance;
> +		e.flags = 0;
> +		*ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
> +	} else {
> +		igt_require(gt == 0); /* Impossible anyway. */
> +		e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
> +		e.instance = 0;
> +		e.flags = I915_EXEC_DEFAULT;
> +		*ctx = intel_ctx_0(i915);

Not sure if we need thecode in the else here, it should only be needed for
antedeluvian kernels. But anyway, leave as is if you want.

Rest everything looks good. These tests can fail on DG2 which have
efficient freq enabled so let's see if we see any failures in pre-merge CI.

Thanks.
--
Ashutosh

> +	}
> +
> +	igt_debug("Using engine %u:%u\n", e.class, e.instance);
> +
> +	return spin_sync(i915, ahnd, *ctx, &e);
> +}
> +
>  static void
> -test_frequency(int gem_fd)
> +test_frequency(int gem_fd, unsigned int gt)
>  {
>	uint32_t min_freq, max_freq, boost_freq;
>	uint64_t val[2], start[2], slept;
> @@ -1548,13 +1654,14 @@ test_frequency(int gem_fd)
>	igt_spin_t *spin;
>	int fd[2], sysfs;
>	uint64_t ahnd = get_reloc_ahnd(gem_fd, 0);
> +	const intel_ctx_t *ctx;
>
> -	sysfs = igt_sysfs_open(gem_fd);
> +	sysfs = igt_sysfs_gt_open(gem_fd, gt);
>	igt_require(sysfs >= 0);
>
> -	min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
> -	max_freq = igt_sysfs_get_u32(sysfs, "gt_RP0_freq_mhz");
> -	boost_freq = igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz");
> +	min_freq = igt_sysfs_get_u32(sysfs, "rps_RPn_freq_mhz");
> +	max_freq = igt_sysfs_get_u32(sysfs, "rps_RP0_freq_mhz");
> +	boost_freq = igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz");
>	igt_info("Frequency: min=%u, max=%u, boost=%u MHz\n",
>		 min_freq, max_freq, boost_freq);
>	igt_require(min_freq > 0 && max_freq > 0 && boost_freq > 0);
> @@ -1567,15 +1674,15 @@ test_frequency(int gem_fd)
>	/*
>	 * Set GPU to min frequency and read PMU counters.
>	 */
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == min_freq);
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", min_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == min_freq);
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", min_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == min_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") == min_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_max_freq_mhz", min_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_max_freq_mhz") == min_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_boost_freq_mhz", min_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz") == min_freq);
>
>	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
> -	spin = spin_sync_flags(gem_fd, ahnd, 0, I915_EXEC_DEFAULT);
> +	spin = spin_sync_gt(gem_fd, ahnd, gt, &ctx);
>
>	slept = pmu_read_multi(fd[0], 2, start);
>	measured_usleep(batch_duration_ns / 1000);
> @@ -1584,6 +1691,7 @@ test_frequency(int gem_fd)
>	min[0] = 1e9*(val[0] - start[0]) / slept;
>	min[1] = 1e9*(val[1] - start[1]) / slept;
>
> +	intel_ctx_destroy(gem_fd, ctx);
>	igt_spin_free(gem_fd, spin);
>	gem_quiescent_gpu(gem_fd); /* Don't leak busy bo into the next phase */
>
> @@ -1592,16 +1700,16 @@ test_frequency(int gem_fd)
>	/*
>	 * Set GPU to max frequency and read PMU counters.
>	 */
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", max_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == max_freq);
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", boost_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == boost_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_max_freq_mhz", max_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_max_freq_mhz") == max_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_boost_freq_mhz", boost_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz") == boost_freq);
>
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", max_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == max_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", max_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") == max_freq);
>
>	gem_quiescent_gpu(gem_fd);
> -	spin = spin_sync_flags(gem_fd, ahnd, 0, I915_EXEC_DEFAULT);
> +	spin = spin_sync_gt(gem_fd, ahnd, gt, &ctx);
>
>	slept = pmu_read_multi(fd[0], 2, start);
>	measured_usleep(batch_duration_ns / 1000);
> @@ -1610,16 +1718,17 @@ test_frequency(int gem_fd)
>	max[0] = 1e9*(val[0] - start[0]) / slept;
>	max[1] = 1e9*(val[1] - start[1]) / slept;
>
> +	intel_ctx_destroy(gem_fd, ctx);
>	igt_spin_free(gem_fd, spin);
>	gem_quiescent_gpu(gem_fd);
>
>	/*
>	 * Restore min/max.
>	 */
> -	igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq);
> -	if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
> +	igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq);
> +	if (igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") != min_freq)
>		igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n",
> -			 min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));
> +			 min_freq, igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz"));
>	close(fd[0]);
>	close(fd[1]);
>	put_ahnd(ahnd);
> @@ -1638,17 +1747,17 @@ test_frequency(int gem_fd)
>  }
>
>  static void
> -test_frequency_idle(int gem_fd)
> +test_frequency_idle(int gem_fd, unsigned int gt)
>  {
>	uint32_t min_freq;
>	uint64_t val[2], start[2], slept;
>	double idle[2];
>	int fd[2], sysfs;
>
> -	sysfs = igt_sysfs_open(gem_fd);
> +	sysfs = igt_sysfs_gt_open(gem_fd, gt);
>	igt_require(sysfs >= 0);
>
> -	min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
> +	min_freq = igt_sysfs_get_u32(sysfs, "rps_RPn_freq_mhz");
>	close(sysfs);
>
>	/* While parked, our convention is to report the GPU at 0Hz */
> @@ -2458,10 +2567,14 @@ igt_main
>	/**
>	 * Test GPU frequency.
>	 */
> -	igt_subtest("frequency")
> -		test_frequency(fd);
> -	igt_subtest("frequency-idle")
> -		test_frequency_idle(fd);
> +	igt_subtest_with_dynamic("frequency") {
> +		for_each_gt(fd, gt, tmp) {
> +			igt_dynamic_f("gt%u", gt)
> +				test_frequency(fd, gt);
> +			igt_dynamic_f("idle-gt%u", gt)
> +				test_frequency_idle(fd, gt);
> +		}
> +	}
>
>	/**
>	 * Test interrupt count reporting.
> --
> 2.34.1
>

[igt-dev] [PATCH i-g-t 04/15] perf_pmu: Quiesce GPU if measuring idle busyness without spinner

[Umesh Nerlige Ramappa]

The assumption in some tests is that the engines are not busy if no
spinners are being run. This is not true in some cases where we see
that the render is busy at the start of the test. Quiesce GPU to wait
for such work to complete before checking for idle busyness.

v2: Move gem_quiescent_gpu to beginning of test (Tvrtko)

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/perf_pmu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 0b1177785..6080c5fdc 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -279,6 +279,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
 	int fd;
 	uint64_t ahnd = get_reloc_ahnd(gem_fd, ctx->id);
 
+	gem_quiescent_gpu(gem_fd);
 	fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
 	if (flags & TEST_BUSY)
@@ -639,6 +640,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
 	int fd[2];
 	uint64_t ahnd = get_reloc_ahnd(gem_fd, ctx->id);
 
+	gem_quiescent_gpu(gem_fd);
 	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
 			   -1);
 	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance),
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 04/15] perf_pmu: Quiesce GPU if measuring idle busyness without spinner

[Dixit, Ashutosh]

On Fri, 05 May 2023 17:55:17 -0700, Umesh Nerlige Ramappa wrote:
>
> The assumption in some tests is that the engines are not busy if no
> spinners are being run. This is not true in some cases where we see
> that the render is busy at the start of the test. Quiesce GPU to wait
> for such work to complete before checking for idle busyness.
>
> v2: Move gem_quiescent_gpu to beginning of test (Tvrtko)

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/i915/perf_pmu.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> index 0b1177785..6080c5fdc 100644
> --- a/tests/i915/perf_pmu.c
> +++ b/tests/i915/perf_pmu.c
> @@ -279,6 +279,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
>	int fd;
>	uint64_t ahnd = get_reloc_ahnd(gem_fd, ctx->id);
>
> +	gem_quiescent_gpu(gem_fd);
>	fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
>	if (flags & TEST_BUSY)
> @@ -639,6 +640,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
>	int fd[2];
>	uint64_t ahnd = get_reloc_ahnd(gem_fd, ctx->id);
>
> +	gem_quiescent_gpu(gem_fd);
>	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
>			   -1);
>	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance),
> --
> 2.34.1
>

[igt-dev] [PATCH i-g-t 05/15] perf_pmu: Use correct pmu config for multi-tile

[Umesh Nerlige Ramappa]

From: Riana Tauro <riana.tauro@intel.com>

Use the correct perf_pmu config for actual and requested frequency in
multi-tile frequency test.

Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/perf_pmu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 6080c5fdc..2d29887e0 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -1670,8 +1670,8 @@ test_frequency(int gem_fd, unsigned int gt)
 	igt_require(max_freq > min_freq);
 	igt_require(boost_freq > min_freq);
 
-	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
+	fd[0] = open_group(gem_fd, __I915_PMU_REQUESTED_FREQUENCY(gt), -1);
+	fd[1] = open_group(gem_fd, __I915_PMU_ACTUAL_FREQUENCY(gt), fd[0]);
 
 	/*
 	 * Set GPU to min frequency and read PMU counters.
@@ -1764,8 +1764,8 @@ test_frequency_idle(int gem_fd, unsigned int gt)
 
 	/* While parked, our convention is to report the GPU at 0Hz */
 
-	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
+	fd[0] = open_group(gem_fd, __I915_PMU_REQUESTED_FREQUENCY(gt), -1);
+	fd[1] = open_group(gem_fd, __I915_PMU_ACTUAL_FREQUENCY(gt), fd[0]);
 
 	gem_quiescent_gpu(gem_fd); /* Be idle! */
 	measured_usleep(2000); /* Wait for timers to cease */
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 05/15] perf_pmu: Use correct pmu config for multi-tile

[Umesh Nerlige Ramappa]

On Fri, May 05, 2023 at 05:55:18PM -0700, Umesh Nerlige Ramappa wrote:
>From: Riana Tauro <riana.tauro@intel.com>
>
>Use the correct perf_pmu config for actual and requested frequency in
>multi-tile frequency test.
>
>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>---
> tests/i915/perf_pmu.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
>diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
>index 6080c5fdc..2d29887e0 100644
>--- a/tests/i915/perf_pmu.c
>+++ b/tests/i915/perf_pmu.c
>@@ -1670,8 +1670,8 @@ test_frequency(int gem_fd, unsigned int gt)
> 	igt_require(max_freq > min_freq);
> 	igt_require(boost_freq > min_freq);
>
>-	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
>-	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
>+	fd[0] = open_group(gem_fd, __I915_PMU_REQUESTED_FREQUENCY(gt), -1);
>+	fd[1] = open_group(gem_fd, __I915_PMU_ACTUAL_FREQUENCY(gt), fd[0]);
>
> 	/*
> 	 * Set GPU to min frequency and read PMU counters.
>@@ -1764,8 +1764,8 @@ test_frequency_idle(int gem_fd, unsigned int gt)
>
> 	/* While parked, our convention is to report the GPU at 0Hz */
>
>-	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
>-	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
>+	fd[0] = open_group(gem_fd, __I915_PMU_REQUESTED_FREQUENCY(gt), -1);
>+	fd[1] = open_group(gem_fd, __I915_PMU_ACTUAL_FREQUENCY(gt), fd[0]);
>
> 	gem_quiescent_gpu(gem_fd); /* Be idle! */
> 	measured_usleep(2000); /* Wait for timers to cease */
>-- 
>2.34.1
>

[igt-dev] [PATCH i-g-t 06/15] intel_gpu_top: Add an array of freq and rc6 counters

[Umesh Nerlige Ramappa]

Since rc6 and frequency events are specific to a tile in multi-tile platforms,
prepare support for multi-tile by storing these events in an array.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index b6827b3de..3d21f25bd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -87,6 +87,7 @@ struct engine_class {
 	unsigned int num_engines;
 };
 
+#define MAX_GTS 4
 struct engines {
 	unsigned int num_engines;
 	unsigned int num_classes;
@@ -106,9 +107,12 @@ struct engines {
 	unsigned int num_imc;
 
 	struct pmu_counter freq_req;
+	struct pmu_counter freq_req_gt[MAX_GTS];
 	struct pmu_counter freq_act;
+	struct pmu_counter freq_act_gt[MAX_GTS];
 	struct pmu_counter irq;
 	struct pmu_counter rc6;
+	struct pmu_counter rc6_gt[MAX_GTS];
 
 	bool discrete;
 	char *device;
-- 
2.34.1

[igt-dev] [PATCH i-g-t 07/15] intel_gpu_top: Determine number of tiles

[Umesh Nerlige Ramappa]

Find out how many tiles are present in the platforms for multi-tile support.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 3d21f25bd..695f57526 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -117,6 +117,8 @@ struct engines {
 	bool discrete;
 	char *device;
 
+	int num_gts;
+
 	/* Do not edit below this line.
 	 * This structure is reallocated every time a new engine is
 	 * found and size is increased by sizeof (engine).
@@ -533,6 +535,25 @@ static void imc_reads_open(struct pmu_counter *pmu, struct engines *engines)
 	imc_open(pmu, "data_reads", engines);
 }
 
+static int get_num_gts(uint64_t type)
+{
+	int fd, cnt;
+
+	errno = 0;
+	for (cnt = 0; cnt < MAX_GTS; cnt++) {
+		fd = igt_perf_open(type, __I915_PMU_REQUESTED_FREQUENCY(cnt));
+		if (fd < 0)
+			break;
+
+		close(fd);
+	}
+	assert(!errno || errno == ENOENT);
+	assert(cnt > 0);
+	errno = 0;
+
+	return cnt;
+}
+
 static int pmu_init(struct engines *engines)
 {
 	unsigned int i;
@@ -541,6 +562,7 @@ static int pmu_init(struct engines *engines)
 
 	engines->fd = -1;
 	engines->num_counters = 0;
+	engines->num_gts = get_num_gts(type);
 
 	engines->irq.config = I915_PMU_INTERRUPTS;
 	fd = _open_pmu(type, engines->num_counters, &engines->irq, engines->fd);
-- 
2.34.1

[igt-dev] [PATCH i-g-t 08/15] intel_gpu_top: Capture freq and rc6 counters from each gt

[Umesh Nerlige Ramappa]

Loop through available gts and store the frequency and rc6 counters.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 695f57526..b0c177329 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -578,6 +578,17 @@ static int pmu_init(struct engines *engines)
 	engines->rc6.config = I915_PMU_RC6_RESIDENCY;
 	_open_pmu(type, engines->num_counters, &engines->rc6, engines->fd);
 
+	for (i = 0; i < engines->num_gts; i++) {
+		engines->freq_req_gt[i].config = __I915_PMU_REQUESTED_FREQUENCY(i);
+		_open_pmu(type, engines->num_counters, &engines->freq_req_gt[i], engines->fd);
+
+		engines->freq_act_gt[i].config = __I915_PMU_ACTUAL_FREQUENCY(i);
+		_open_pmu(type, engines->num_counters, &engines->freq_act_gt[i], engines->fd);
+
+		engines->rc6_gt[i].config = __I915_PMU_RC6_RESIDENCY(i);
+		_open_pmu(type, engines->num_counters, &engines->rc6_gt[i], engines->fd);
+	}
+
 	for (i = 0; i < engines->num_engines; i++) {
 		struct engine *engine = engine_ptr(engines, i);
 		struct {
@@ -679,6 +690,12 @@ static void pmu_sample(struct engines *engines)
 	engines->ts.prev = engines->ts.cur;
 	engines->ts.cur = pmu_read_multi(engines->fd, num_val, val);
 
+	for (i = 0; i < engines->num_gts; i++) {
+		update_sample(&engines->freq_req_gt[i], val);
+		update_sample(&engines->freq_act_gt[i], val);
+		update_sample(&engines->rc6_gt[i], val);
+	}
+
 	update_sample(&engines->freq_req, val);
 	update_sample(&engines->freq_act, val);
 	update_sample(&engines->irq, val);
-- 
2.34.1

[igt-dev] [PATCH i-g-t 09/15] intel_gpu_top: Switch pmu_counter to use aggregated values

[Umesh Nerlige Ramappa]

Aggregate gt specific values for freq and rc6 counters.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 49 +++++++++++++++++++++++++++++++++----------
 1 file changed, 38 insertions(+), 11 deletions(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index b0c177329..d995c39b9 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -554,6 +554,26 @@ static int get_num_gts(uint64_t type)
 	return cnt;
 }
 
+static void init_aggregate_counters(struct engines *engines)
+{
+	struct pmu_counter *pmu;
+
+	pmu = &engines->freq_req;
+	pmu->type = igt_perf_type_id(engines->device);
+	pmu->config = I915_PMU_REQUESTED_FREQUENCY;
+	pmu->present = true;
+
+	pmu = &engines->freq_act;
+	pmu->type = igt_perf_type_id(engines->device);
+	pmu->config = I915_PMU_ACTUAL_FREQUENCY;
+	pmu->present = true;
+
+	pmu = &engines->rc6;
+	pmu->type = igt_perf_type_id(engines->device);
+	pmu->config = I915_PMU_RC6_RESIDENCY;
+	pmu->present = true;
+}
+
 static int pmu_init(struct engines *engines)
 {
 	unsigned int i;
@@ -569,14 +589,7 @@ static int pmu_init(struct engines *engines)
 	if (fd < 0)
 		return -1;
 
-	engines->freq_req.config = I915_PMU_REQUESTED_FREQUENCY;
-	_open_pmu(type, engines->num_counters, &engines->freq_req, engines->fd);
-
-	engines->freq_act.config = I915_PMU_ACTUAL_FREQUENCY;
-	_open_pmu(type, engines->num_counters, &engines->freq_act, engines->fd);
-
-	engines->rc6.config = I915_PMU_RC6_RESIDENCY;
-	_open_pmu(type, engines->num_counters, &engines->rc6, engines->fd);
+	init_aggregate_counters(engines);
 
 	for (i = 0; i < engines->num_gts; i++) {
 		engines->freq_req_gt[i].config = __I915_PMU_REQUESTED_FREQUENCY(i);
@@ -692,14 +705,28 @@ static void pmu_sample(struct engines *engines)
 
 	for (i = 0; i < engines->num_gts; i++) {
 		update_sample(&engines->freq_req_gt[i], val);
+		engines->freq_req.val.cur += engines->freq_req_gt[i].val.cur;
+		engines->freq_req.val.prev += engines->freq_req_gt[i].val.prev;
+
 		update_sample(&engines->freq_act_gt[i], val);
+		engines->freq_act.val.cur += engines->freq_act_gt[i].val.cur;
+		engines->freq_act.val.prev += engines->freq_act_gt[i].val.prev;
+
 		update_sample(&engines->rc6_gt[i], val);
+		engines->rc6.val.cur += engines->rc6_gt[i].val.cur;
+		engines->rc6.val.prev += engines->rc6_gt[i].val.prev;
 	}
 
-	update_sample(&engines->freq_req, val);
-	update_sample(&engines->freq_act, val);
+	engines->freq_req.val.cur /= engines->num_gts;
+	engines->freq_req.val.prev /= engines->num_gts;
+
+	engines->freq_act.val.cur /= engines->num_gts;
+	engines->freq_act.val.prev /= engines->num_gts;
+
+	engines->rc6.val.cur /= engines->num_gts;
+	engines->rc6.val.prev /= engines->num_gts;
+
 	update_sample(&engines->irq, val);
-	update_sample(&engines->rc6, val);
 
 	for (i = 0; i < engines->num_engines; i++) {
 		struct engine *engine = engine_ptr(engines, i);
-- 
2.34.1

[igt-dev] [PATCH i-g-t 10/15] intel_gpu_top: Add definitions for gt-specific items and groups

[Umesh Nerlige Ramappa]

Prepare to pass a modified groups array to print_groups by defining
separate items and groups for each gt.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 44 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index d995c39b9..63ce9fade 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1854,6 +1854,30 @@ print_header(const struct igt_device_card *card,
 		.display_name = "Freq MHz",
 		.items = freq_items,
 	};
+	struct cnt_item freq_items_gt[] = {
+		{ &engines->freq_req_gt[0], 6, 0, 1.0, t, 1, "requested", "req" },
+		{ &engines->freq_act_gt[0], 6, 0, 1.0, t, 1, "actual", "act" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "MHz" },
+		{ },
+		{ &engines->freq_req_gt[1], 6, 0, 1.0, t, 1, "requested", "req" },
+		{ &engines->freq_act_gt[1], 6, 0, 1.0, t, 1, "actual", "act" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "MHz" },
+		{ },
+		{ &engines->freq_req_gt[2], 6, 0, 1.0, t, 1, "requested", "req" },
+		{ &engines->freq_act_gt[2], 6, 0, 1.0, t, 1, "actual", "act" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "MHz" },
+		{ },
+		{ &engines->freq_req_gt[3], 6, 0, 1.0, t, 1, "requested", "req" },
+		{ &engines->freq_act_gt[3], 6, 0, 1.0, t, 1, "actual", "act" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "MHz" },
+		{ },
+	};
+	struct cnt_group freq_group_gt[MAX_GTS] = {
+		{ .name = "frequency-gt0", .display_name = "Freq GT0 MHz", .items = &freq_items_gt[0] },
+		{ .name = "frequency-gt1", .display_name = "Freq GT1 MHz", .items = &freq_items_gt[4] },
+		{ .name = "frequency-gt2", .display_name = "Freq GT2 MHz", .items = &freq_items_gt[8] },
+		{ .name = "frequency-gt3", .display_name = "Freq GT3 MHz", .items = &freq_items_gt[12] },
+	};
 	struct cnt_item irq_items[] = {
 		{ &engines->irq, 8, 0, 1.0, t, 1, "count", "/s" },
 		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "irq/s" },
@@ -1874,6 +1898,26 @@ print_header(const struct igt_device_card *card,
 		.display_name = "RC6",
 		.items = rc6_items,
 	};
+	struct cnt_item rc6_items_gt[] = {
+		{ &engines->rc6_gt[0], 8, 0, 1e9, t, 100, "value", "%" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "%" },
+		{ },
+		{ &engines->rc6_gt[1], 8, 0, 1e9, t, 100, "value", "%" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "%" },
+		{ },
+		{ &engines->rc6_gt[2], 8, 0, 1e9, t, 100, "value", "%" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "%" },
+		{ },
+		{ &engines->rc6_gt[3], 8, 0, 1e9, t, 100, "value", "%" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "%" },
+		{ },
+	};
+	struct cnt_group rc6_group_gt[MAX_GTS] = {
+		{ .name = "rc6-gt0", .display_name = "RC6 GT0", .items = &rc6_items_gt[0] },
+		{ .name = "rc6-gt1", .display_name = "RC6 GT1", .items = &rc6_items_gt[3] },
+		{ .name = "rc6-gt2", .display_name = "RC6 GT2", .items = &rc6_items_gt[6] },
+		{ .name = "rc6-gt3", .display_name = "RC6 GT3", .items = &rc6_items_gt[9] },
+	};
 	struct cnt_item power_items[] = {
 		{ &engines->r_gpu, 4, 2, 1.0, t, engines->r_gpu.scale, "GPU", "gpu" },
 		{ &engines->r_pkg, 4, 2, 1.0, t, engines->r_pkg.scale, "Package", "pkg" },
-- 
2.34.1

[igt-dev] [PATCH i-g-t 11/15] intel_gpu_top: Bump up size of groups to accomodate multi-gt

[Umesh Nerlige Ramappa]

Create more space in groups to add gt specific freq and rc6 groups.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 63ce9fade..87d869802 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1929,7 +1929,13 @@ print_header(const struct igt_device_card *card,
 		.display_name = "Power W",
 		.items = power_items,
 	};
-	struct cnt_group *groups[] = {
+	/*
+	 * Array size calculation:
+	 * One group each for period, irq, power, NULL = 4
+	 * One group per gt for freq = MAX_GTS
+	 * One group per gt for rc6  = MAX_GTS
+	 */
+	struct cnt_group *groups[4 + MAX_GTS + MAX_GTS] = {
 		&period_group,
 		&freq_group,
 		&irq_group,
-- 
2.34.1

[igt-dev] [PATCH i-g-t 12/15] intel_gpu_top: Increase visibility for class_view

[Umesh Nerlige Ramappa]

Some future changes may access class_view before it's declared, so move
it to top

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 87d869802..4d0aeee16 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -129,6 +129,7 @@ struct engines {
 };
 
 static struct termios termios_orig;
+static bool class_view;
 
 __attribute__((format(scanf,3,4)))
 static int igt_sysfs_scanf(int dir, const char *attr, const char *fmt, ...)
@@ -2054,8 +2055,6 @@ print_imc(struct engines *engines, double t, int lines, int con_w, int con_h)
 	return lines;
 }
 
-static bool class_view;
-
 static int
 print_engines_header(struct engines *engines, double t,
 		     int lines, int con_w, int con_h)
-- 
2.34.1

[igt-dev] [PATCH i-g-t 13/15] intel_gpu_top: Show gt specific values if requested

[Umesh Nerlige Ramappa]

On multi-gt platforms, the aggregate values are displayed as default. If
user passes -p (physical) option for these platforms, show gt specific
counter values.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 4d0aeee16..8bcca67a6 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1944,6 +1944,26 @@ print_header(const struct igt_device_card *card,
 		&power_group,
 		NULL
 	};
+	int i;
+
+	/*
+	 * If we have multi-gt and the user has specified -p options, show gt
+	 * specific values.
+	 */
+	if (!class_view && engines->num_gts > 1) {
+		int j = 0;
+
+		groups[j++] = &period_group;
+		for (i = 0; i < engines->num_gts; i++)
+			groups[j++] = &freq_group_gt[i];
+
+		groups[j++] = &irq_group;
+		for (i = 0; i < engines->num_gts; i++)
+			groups[j++] = &rc6_group_gt[i];
+
+		groups[j++] = &power_group;
+		groups[j++] = NULL;
+	}
 
 	if (output_mode != JSON)
 		memmove(&groups[0], &groups[1],
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 13/15] intel_gpu_top: Show gt specific values if requested

[Tvrtko Ursulin]

On 06/05/2023 01:55, Umesh Nerlige Ramappa wrote:
> On multi-gt platforms, the aggregate values are displayed as default. If
> user passes -p (physical) option for these platforms, show gt specific
> counter values.
> 
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>   tools/intel_gpu_top.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 4d0aeee16..8bcca67a6 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -1944,6 +1944,26 @@ print_header(const struct igt_device_card *card,
>   		&power_group,
>   		NULL
>   	};
> +	int i;
> +
> +	/*
> +	 * If we have multi-gt and the user has specified -p options, show gt
> +	 * specific values.
> +	 */
> +	if (!class_view && engines->num_gts > 1) {
> +		int j = 0;
> +
> +		groups[j++] = &period_group;
> +		for (i = 0; i < engines->num_gts; i++)
> +			groups[j++] = &freq_group_gt[i];
> +
> +		groups[j++] = &irq_group;
> +		for (i = 0; i < engines->num_gts; i++)
> +			groups[j++] = &rc6_group_gt[i];
> +
> +		groups[j++] = &power_group;
> +		groups[j++] = NULL;
> +	}
>   
>   	if (output_mode != JSON)
>   		memmove(&groups[0], &groups[1],

This works fine. One day we can think about how to make the setup one 
time. Like have two pre-configured groups arrays and then just select 
the right one here based on class_view.

Regards,

Tvrtko

[igt-dev] [PATCH i-g-t 14/15] intel_gpu_top: Reduce one level of indent

[Umesh Nerlige Ramappa]

Prepare to display gt specific items in INTERACTIVE mode with the -p
option. An additional for loop will push code more towards right, so
reduce one level of indent.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 74 ++++++++++++++++++++++---------------------
 1 file changed, 38 insertions(+), 36 deletions(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 8bcca67a6..0acc81e9e 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1944,7 +1944,7 @@ print_header(const struct igt_device_card *card,
 		&power_group,
 		NULL
 	};
-	int i;
+	int rem, i;
 
 	/*
 	 * If we have multi-gt and the user has specified -p options, show gt
@@ -1971,51 +1971,53 @@ print_header(const struct igt_device_card *card,
 
 	*consumed = print_groups(groups);
 
-	if (output_mode == INTERACTIVE) {
-		int rem = con_w;
+	if (output_mode != INTERACTIVE)
+		return lines;
 
-		printf("\033[H\033[J");
+	/* INTERACTIVE MODE */
+	rem = con_w;
 
-		lines = print_header_token(NULL, lines, con_w, con_h, &rem,
-					   "intel-gpu-top:");
+	printf("\033[H\033[J");
 
-		lines = print_header_token(" ", lines, con_w, con_h, &rem,
-					   "%s", codename);
+	lines = print_header_token(NULL, lines, con_w, con_h, &rem,
+				   "intel-gpu-top:");
 
-		lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
-					   "%s", card->card);
+	lines = print_header_token(" ", lines, con_w, con_h, &rem,
+				   "%s", codename);
 
-		lines = print_header_token(" - ", lines, con_w, con_h, &rem,
-					   "%s/%s MHz",
-					   freq_items[1].buf,
-					   freq_items[0].buf);
+	lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
+				   "%s", card->card);
 
-		lines = print_header_token("; ", lines, con_w, con_h, &rem,
-					   "%s%% RC6",
-					   rc6_items[0].buf);
+	lines = print_header_token(" - ", lines, con_w, con_h, &rem,
+				   "%s/%s MHz",
+				   freq_items[1].buf,
+				   freq_items[0].buf);
 
-		if (engines->r_gpu.present) {
-			lines = print_header_token("; ", lines, con_w, con_h,
-						   &rem,
-						   "%s/%s W",
-						   power_items[0].buf,
-						   power_items[1].buf);
-		}
+	lines = print_header_token("; ", lines, con_w, con_h, &rem,
+				   "%s%% RC6",
+				   rc6_items[0].buf);
 
-		lines = print_header_token("; ", lines, con_w, con_h, &rem,
-					   "%s irqs/s",
-					   irq_items[0].buf);
+	if (engines->r_gpu.present) {
+		lines = print_header_token("; ", lines, con_w, con_h,
+					   &rem,
+					   "%s/%s W",
+					   power_items[0].buf,
+					   power_items[1].buf);
+	}
 
-		if (lines++ < con_h)
-			printf("\n");
+	lines = print_header_token("; ", lines, con_w, con_h, &rem,
+				   "%s irqs/s",
+				   irq_items[0].buf);
 
-		if (lines++ < con_h) {
-			if (header_msg) {
-				printf(" >>> %s\n", header_msg);
-				header_msg = NULL;
-			} else {
-				printf("\n");
-			}
+	if (lines++ < con_h)
+		printf("\n");
+
+	if (lines++ < con_h) {
+		if (header_msg) {
+			printf(" >>> %s\n", header_msg);
+			header_msg = NULL;
+		} else {
+			printf("\n");
 		}
 	}
 
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 14/15] intel_gpu_top: Reduce one level of indent

[Tvrtko Ursulin]

On 06/05/2023 01:55, Umesh Nerlige Ramappa wrote:
> Prepare to display gt specific items in INTERACTIVE mode with the -p
> option. An additional for loop will push code more towards right, so
> reduce one level of indent.
> 
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>   tools/intel_gpu_top.c | 74 ++++++++++++++++++++++---------------------
>   1 file changed, 38 insertions(+), 36 deletions(-)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 8bcca67a6..0acc81e9e 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -1944,7 +1944,7 @@ print_header(const struct igt_device_card *card,
>   		&power_group,
>   		NULL
>   	};
> -	int i;
> +	int rem, i;
>   
>   	/*
>   	 * If we have multi-gt and the user has specified -p options, show gt
> @@ -1971,51 +1971,53 @@ print_header(const struct igt_device_card *card,
>   
>   	*consumed = print_groups(groups);
>   
> -	if (output_mode == INTERACTIVE) {
> -		int rem = con_w;
> +	if (output_mode != INTERACTIVE)
> +		return lines;

Yeah this is better in any case since it correctly expresses the 
either-or flow.

Regards,

Tvrtko

>   
> -		printf("\033[H\033[J");
> +	/* INTERACTIVE MODE */
> +	rem = con_w;
>   
> -		lines = print_header_token(NULL, lines, con_w, con_h, &rem,
> -					   "intel-gpu-top:");
> +	printf("\033[H\033[J");
>   
> -		lines = print_header_token(" ", lines, con_w, con_h, &rem,
> -					   "%s", codename);
> +	lines = print_header_token(NULL, lines, con_w, con_h, &rem,
> +				   "intel-gpu-top:");
>   
> -		lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
> -					   "%s", card->card);
> +	lines = print_header_token(" ", lines, con_w, con_h, &rem,
> +				   "%s", codename);
>   
> -		lines = print_header_token(" - ", lines, con_w, con_h, &rem,
> -					   "%s/%s MHz",
> -					   freq_items[1].buf,
> -					   freq_items[0].buf);
> +	lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
> +				   "%s", card->card);
>   
> -		lines = print_header_token("; ", lines, con_w, con_h, &rem,
> -					   "%s%% RC6",
> -					   rc6_items[0].buf);
> +	lines = print_header_token(" - ", lines, con_w, con_h, &rem,
> +				   "%s/%s MHz",
> +				   freq_items[1].buf,
> +				   freq_items[0].buf);
>   
> -		if (engines->r_gpu.present) {
> -			lines = print_header_token("; ", lines, con_w, con_h,
> -						   &rem,
> -						   "%s/%s W",
> -						   power_items[0].buf,
> -						   power_items[1].buf);
> -		}
> +	lines = print_header_token("; ", lines, con_w, con_h, &rem,
> +				   "%s%% RC6",
> +				   rc6_items[0].buf);
>   
> -		lines = print_header_token("; ", lines, con_w, con_h, &rem,
> -					   "%s irqs/s",
> -					   irq_items[0].buf);
> +	if (engines->r_gpu.present) {
> +		lines = print_header_token("; ", lines, con_w, con_h,
> +					   &rem,
> +					   "%s/%s W",
> +					   power_items[0].buf,
> +					   power_items[1].buf);
> +	}
>   
> -		if (lines++ < con_h)
> -			printf("\n");
> +	lines = print_header_token("; ", lines, con_w, con_h, &rem,
> +				   "%s irqs/s",
> +				   irq_items[0].buf);
>   
> -		if (lines++ < con_h) {
> -			if (header_msg) {
> -				printf(" >>> %s\n", header_msg);
> -				header_msg = NULL;
> -			} else {
> -				printf("\n");
> -			}
> +	if (lines++ < con_h)
> +		printf("\n");
> +
> +	if (lines++ < con_h) {
> +		if (header_msg) {
> +			printf(" >>> %s\n", header_msg);
> +			header_msg = NULL;
> +		} else {
> +			printf("\n");
>   		}
>   	}
>   

[igt-dev] [PATCH i-g-t 15/15] intel_gpu_top: Add gt specific values to header in interactive mode

[Umesh Nerlige Ramappa]

If -p options is specified in INTERACTIVE mode, show the gt specific
values.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 33 +++++++++++++++++++++++++--------
 1 file changed, 25 insertions(+), 8 deletions(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 0acc81e9e..7018499c7 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1988,14 +1988,31 @@ print_header(const struct igt_device_card *card,
 	lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
 				   "%s", card->card);
 
-	lines = print_header_token(" - ", lines, con_w, con_h, &rem,
-				   "%s/%s MHz",
-				   freq_items[1].buf,
-				   freq_items[0].buf);
-
-	lines = print_header_token("; ", lines, con_w, con_h, &rem,
-				   "%s%% RC6",
-				   rc6_items[0].buf);
+	if (class_view || engines->num_gts == 1) {
+		lines = print_header_token(" - ", lines, con_w, con_h, &rem,
+					   "%s/%s MHz",
+					   freq_items[1].buf,
+					   freq_items[0].buf);
+
+		lines = print_header_token("; ", lines, con_w, con_h, &rem,
+					   "%s%% RC6",
+					   rc6_items[0].buf);
+	} else {
+		for (i = 0; i < engines->num_gts; i++) {
+			const char *cont = !i ? " - ": "; ";
+
+			lines = print_header_token(cont, lines, con_w, con_h, &rem,
+						   "%s/%s MHz(gt%d)",
+						   freq_items_gt[i * 4 + 1].buf,
+						   freq_items_gt[i * 4 + 0].buf,
+						   i);
+
+			lines = print_header_token("; ", lines, con_w, con_h, &rem,
+						   "%s%% RC6(gt%d)",
+						   rc6_items_gt[i * 3].buf,
+						   i);
+		}
+	}
 
 	if (engines->r_gpu.present) {
 		lines = print_header_token("; ", lines, con_w, con_h,
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 15/15] intel_gpu_top: Add gt specific values to header in interactive mode

[Tvrtko Ursulin]

On 06/05/2023 01:55, Umesh Nerlige Ramappa wrote:
> If -p options is specified in INTERACTIVE mode, show the gt specific
> values.
> 
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>   tools/intel_gpu_top.c | 33 +++++++++++++++++++++++++--------
>   1 file changed, 25 insertions(+), 8 deletions(-)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 0acc81e9e..7018499c7 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -1988,14 +1988,31 @@ print_header(const struct igt_device_card *card,
>   	lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
>   				   "%s", card->card);
>   
> -	lines = print_header_token(" - ", lines, con_w, con_h, &rem,
> -				   "%s/%s MHz",
> -				   freq_items[1].buf,
> -				   freq_items[0].buf);
> -
> -	lines = print_header_token("; ", lines, con_w, con_h, &rem,
> -				   "%s%% RC6",
> -				   rc6_items[0].buf);
> +	if (class_view || engines->num_gts == 1) {
> +		lines = print_header_token(" - ", lines, con_w, con_h, &rem,
> +					   "%s/%s MHz",
> +					   freq_items[1].buf,
> +					   freq_items[0].buf);
> +
> +		lines = print_header_token("; ", lines, con_w, con_h, &rem,
> +					   "%s%% RC6",
> +					   rc6_items[0].buf);
> +	} else {
> +		for (i = 0; i < engines->num_gts; i++) {
> +			const char *cont = !i ? " - ": "; ";
> +
> +			lines = print_header_token(cont, lines, con_w, con_h, &rem,
> +						   "%s/%s MHz(gt%d)",
> +						   freq_items_gt[i * 4 + 1].buf,
> +						   freq_items_gt[i * 4 + 0].buf,
> +						   i);
> +
> +			lines = print_header_token("; ", lines, con_w, con_h, &rem,
> +						   "%s%% RC6(gt%d)",
> +						   rc6_items_gt[i * 3].buf,
> +						   i);
> +		}
> +	}
>   
>   	if (engines->r_gpu.present) {
>   		lines = print_header_token("; ", lines, con_w, con_h,

Series was a super easy read, thanks for that! Pretty much r-b for the 
lot from me but I would just like to visualize how the output looks like 
first. Would you mind pasting some examples for all the modes?

Regards,

Tvrtko

Re: [igt-dev] [PATCH i-g-t 15/15] intel_gpu_top: Add gt specific values to header in interactive mode

[Umesh Nerlige Ramappa]

[-- Attachment #1: Type: text/plain, Size: 2342 bytes --]

On Wed, May 10, 2023 at 09:46:53AM +0100, Tvrtko Ursulin wrote:
>
>On 06/05/2023 01:55, Umesh Nerlige Ramappa wrote:
>>If -p options is specified in INTERACTIVE mode, show the gt specific
>>values.
>>
>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>---
>>  tools/intel_gpu_top.c | 33 +++++++++++++++++++++++++--------
>>  1 file changed, 25 insertions(+), 8 deletions(-)
>>
>>diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
>>index 0acc81e9e..7018499c7 100644
>>--- a/tools/intel_gpu_top.c
>>+++ b/tools/intel_gpu_top.c
>>@@ -1988,14 +1988,31 @@ print_header(const struct igt_device_card *card,
>>  	lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
>>  				   "%s", card->card);
>>-	lines = print_header_token(" - ", lines, con_w, con_h, &rem,
>>-				   "%s/%s MHz",
>>-				   freq_items[1].buf,
>>-				   freq_items[0].buf);
>>-
>>-	lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>-				   "%s%% RC6",
>>-				   rc6_items[0].buf);
>>+	if (class_view || engines->num_gts == 1) {
>>+		lines = print_header_token(" - ", lines, con_w, con_h, &rem,
>>+					   "%s/%s MHz",
>>+					   freq_items[1].buf,
>>+					   freq_items[0].buf);
>>+
>>+		lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>+					   "%s%% RC6",
>>+					   rc6_items[0].buf);
>>+	} else {
>>+		for (i = 0; i < engines->num_gts; i++) {
>>+			const char *cont = !i ? " - ": "; ";
>>+
>>+			lines = print_header_token(cont, lines, con_w, con_h, &rem,
>>+						   "%s/%s MHz(gt%d)",
>>+						   freq_items_gt[i * 4 + 1].buf,
>>+						   freq_items_gt[i * 4 + 0].buf,
>>+						   i);
>>+
>>+			lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>+						   "%s%% RC6(gt%d)",
>>+						   rc6_items_gt[i * 3].buf,
>>+						   i);
>>+		}
>>+	}
>>  	if (engines->r_gpu.present) {
>>  		lines = print_header_token("; ", lines, con_w, con_h,
>
>Series was a super easy read, thanks for that! Pretty much r-b for the 
>lot from me but I would just like to visualize how the output looks 
>like first. Would you mind pasting some examples for all the modes?

great, I am attaching the outputs in text files for MTL and DG2 here, 
hope that is visible. If not, I can paste it in pastebin.

MTL shows the gt specific changes. DG2 is single tile, so there are no 
changes.

Thanks,
Umesh
>
>Regards,
>
>Tvrtko

[-- Attachment #2: mtl_pmu.txt --]
[-- Type: text/plain, Size: 5535 bytes --]

> sudo ./intel_gpu_top -l
 Freq MHz      IRQ RC6     Power W             RCS             BCS             VCS            VECS             CCS
 req  act       /s   %   gpu   pkg       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa
   0    0       39 100  0.09 12.24    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0
   0    0        0 100  0.00  5.01    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0
   0    0        0 100  0.00  4.94    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0

> sudo ./intel_gpu_top -l -p
 Freq GT0 MHz  Freq GT1 MHz      IRQ  RC6 GT0  RC6 GT1     Power W           RCS/0           BCS/0           VCS/0           VCS/1          VECS/0           CCS/0
   req    act    req    act       /s        %        %   gpu   pkg       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa
     0      0      0      0       38      100      100  0.00 11.81    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0
     0      0      0      0        0      100      100  0.00  4.97    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0
     0      0      0      0        0      100      100  0.00  4.94    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0

> sudo ./intel_gpu_top -J
[

{
        "period": {
                "duration": 27.774630,
                "unit": "ms"
        },
        "frequency": {
                "requested": 0.000000,
                "actual": 0.000000,
                "unit": "MHz"
        },
        "interrupts": {
                "count": 36.004080,
                "unit": "irq/s"
        },
        "rc6": {
                "value": 100.000000,
                "unit": "%"
        },
        "power": {
                "GPU": 0.065925,
                "Package": 11.444656,
                "unit": "W"
        },
        "engines": {
                "Render/3D": {
                        "busy": 0.000000,
                        "sema": 0.000000,
                        "wait": 0.000000,
                        "unit": "%"
                },
...

> sudo ./intel_gpu_top -J -p
[

{
        "period": {
                "duration": 26.035037,
                "unit": "ms"
        },
        "frequency-gt0": {
                "requested": 0.000000,
                "actual": 0.000000,
                "unit": "MHz"
        },
        "frequency-gt1": {
                "requested": 0.000000,
                "actual": 0.000000,
                "unit": "MHz"
        },
        "interrupts": {
                "count": 38.409778,
                "unit": "irq/s"
        },
        "rc6-gt0": {
                "value": 100.000000,
                "unit": "%"
        },
        "rc6-gt1": {
                "value": 100.000000,
                "unit": "%"
        },
        "power": {
                "GPU": 0.000000,
                "Package": 12.335953,
                "unit": "W"
        },
        "engines": {
                "Render/3D/0": {
                        "busy": 0.000000,
                        "sema": 0.000000,
                        "wait": 0.000000,
                        "unit": "%"
                },
...

> sudo ./intel_gpu_top -c
Freq MHz req,Freq MHz act,IRQ /s,RC6 %,Power W gpu,Power W pkg,RCS %,RCS se,RCS wa,BCS %,BCS se,BCS wa,VCS %,VCS se,VCS wa,VECS %,VECS se,VECS wa,CCS %,CCS se,CCS wa
0.000000,0.000000,37.859083,100.000000,0.000000,12.096698,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000
0.000000,0.000000,0.000000,100.000000,0.000000,5.024299,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000
0.000000,0.000000,0.000000,100.000000,0.000000,4.988727,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000

> sudo ./intel_gpu_top -c -p
Freq GT0 MHz req,Freq GT0 MHz act,Freq GT1 MHz req,Freq GT1 MHz act,IRQ /s,RC6 GT0 %,RC6 GT1 %,Power W gpu,Power W pkg,RCS/0 %,RCS/0 se,RCS/0 wa,BCS/0 %,BCS/0 se,BCS/0 wa,VCS/0 %,VCS/0 se,VCS/0 wa,VCS/1 %,VCS/1 se,VCS/1 wa,VECS/0 %,VECS/0 se,VECS/0 wa,CCS/0 %,CCS/0 se,CCS/0 wa
0.000000,0.000000,0.000000,0.000000,37.173657,99.998777,99.997810,0.068067,11.337693,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000
0.000000,0.000000,0.000000,0.000000,0.000000,100.000000,100.000000,0.000000,5.041599,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000
0.000000,0.000000,0.000000,0.000000,0.000000,100.000000,100.000000,0.000000,5.008404,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000

> sudo ./intel_gpu_top

intel-gpu-top: Intel Meteorlake (Gen12) @ /dev/dri/card0 -    0/   0 MHz; 100% RC6;  0.00/ 4.99 W;        0 irqs/s
...

> sudo ./intel_gpu_top -p

intel-gpu-top: Intel Meteorlake (Gen12) @ /dev/dri/card0 -      0/     0 MHz(gt0);      100% RC6(gt0);      0/     0 MHz(gt1);      100% RC6(gt1);  0.00/ 4.98 W;        0 irqs/s
...


[-- Attachment #3: dg2_pmu.txt --]
[-- Type: text/plain, Size: 5695 bytes --]

> sudo ./intel_gpu_top -l
 Freq MHz      IRQ RC6     IMC MiB/s             RCS             BCS             VCS            VECS             CCS
 req  act       /s   %     rd     wr       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa
   0    0      195 100    144     37    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0
   0    0      142 100     25      6    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0
   0    0        0 100     85      4    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0

> sudo ./intel_gpu_top -l -p
 Freq MHz      IRQ RC6     IMC MiB/s           RCS/0           BCS/0           VCS/0           VCS/1          VECS/0          VECS/1           CCS/0           CCS/1           CCS/2           CCS/3
 req  act       /s   %     rd     wr       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa       %  se  wa
   0    0        0 100    314     55    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0
   0    0        0 100     91      7    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0
   0    0        0 100     92      5    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0    0.00   0   0

> sudo ./intel_gpu_top -J
[

{
        "period": {
                "duration": 25.839066,
                "unit": "ms"
        },
        "frequency": {
                "requested": 0.000000,
                "actual": 0.000000,
                "unit": "MHz"
        },
        "interrupts": {
                "count": 232.206536,
                "unit": "irq/s"
        },
        "rc6": {
                "value": 100.000000,
                "unit": "%"
        },
        "imc-bandwidth": {
                "reads": 299.149216,
                "writes": 20.748924,
                "unit": "MiB/s"
        },
        "engines": {
                "Render/3D": {
                        "busy": 0.000000,
                        "sema": 0.000000,
                        "wait": 0.000000,
                        "unit": "%"
                },
...

> sudo ./intel_gpu_top -J -p
[

{
        "period": {
                "duration": 24.558506,
                "unit": "ms"
        },
        "frequency": {
                "requested": 0.000000,
                "actual": 0.000000,
                "unit": "MHz"
        },
        "interrupts": {
                "count": 0.000000,
                "unit": "irq/s"
        },
        "rc6": {
                "value": 100.000000,
                "unit": "%"
        },
        "imc-bandwidth": {
                "reads": 309.006790,
                "writes": 53.386643,
                "unit": "MiB/s"
        },
        "engines": {
                "Render/3D/0": {
                        "busy": 0.000000,
                        "sema": 0.000000,
                        "wait": 0.000000,
                        "unit": "%"
                },
...

> sudo ./intel_gpu_top -c
Freq MHz req,Freq MHz act,IRQ /s,RC6 %,IMC MiB/s rd,IMC MiB/s wr,RCS %,RCS se,RCS wa,BCS %,BCS se,BCS wa,VCS %,VCS se,VCS wa,VECS %,VECS se,VECS wa,CCS %,CCS se,CCS wa
0.000000,0.000000,197.280107,100.000000,330.786144,24.573318,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000
0.000000,0.000000,149.410773,100.000000,23.879837,3.148010,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000
0.000000,0.000000,0.000000,100.000000,101.882497,5.109333,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000

> sudo ./intel_gpu_top -c -p
Freq MHz req,Freq MHz act,IRQ /s,RC6 %,IMC MiB/s rd,IMC MiB/s wr,RCS/0 %,RCS/0 se,RCS/0 wa,BCS/0 %,BCS/0 se,BCS/0 wa,VCS/0 %,VCS/0 se,VCS/0 wa,VCS/1 %,VCS/1 se,VCS/1 wa,VECS/0 %,VECS/0 se,VECS/0 wa,VECS/1 %,VECS/1 se,VECS/1 wa,CCS/0 %,CCS/0 se,CCS/0 wa,CCS/1 %,CCS/1 se,CCS/1 wa,CCS/2 %,CCS/2 se,CCS/2 wa,CCS/3 %,CCS/3 se,CCS/3 wa
0.000000,0.000000,0.000000,100.000000,340.977673,60.574177,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000
0.000000,0.000000,0.000000,100.000000,88.193030,6.309502,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000
0.000000,0.000000,0.000000,100.000000,89.373431,4.450919,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000,0.000000

> sudo ./intel_gpu_top

intel-gpu-top: Intel Dg2 (Gen12) @ /dev/dri/card0 -    0/   0 MHz; 100% RC6;        0 irqs/s
...

> sudo ./intel_gpu_top -p

intel-gpu-top: Intel Dg2 (Gen12) @ /dev/dri/card0 -    0/   0 MHz; 100% RC6;        0 irqs/s
...

Re: [igt-dev] [PATCH i-g-t 15/15] intel_gpu_top: Add gt specific values to header in interactive mode

[Tvrtko Ursulin]

On 10/05/2023 23:14, Umesh Nerlige Ramappa wrote:
> On Wed, May 10, 2023 at 09:46:53AM +0100, Tvrtko Ursulin wrote:
>>
>> On 06/05/2023 01:55, Umesh Nerlige Ramappa wrote:
>>> If -p options is specified in INTERACTIVE mode, show the gt specific
>>> values.
>>>
>>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>> ---
>>>  tools/intel_gpu_top.c | 33 +++++++++++++++++++++++++--------
>>>  1 file changed, 25 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
>>> index 0acc81e9e..7018499c7 100644
>>> --- a/tools/intel_gpu_top.c
>>> +++ b/tools/intel_gpu_top.c
>>> @@ -1988,14 +1988,31 @@ print_header(const struct igt_device_card *card,
>>>      lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
>>>                     "%s", card->card);
>>> -    lines = print_header_token(" - ", lines, con_w, con_h, &rem,
>>> -                   "%s/%s MHz",
>>> -                   freq_items[1].buf,
>>> -                   freq_items[0].buf);
>>> -
>>> -    lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>> -                   "%s%% RC6",
>>> -                   rc6_items[0].buf);
>>> +    if (class_view || engines->num_gts == 1) {
>>> +        lines = print_header_token(" - ", lines, con_w, con_h, &rem,
>>> +                       "%s/%s MHz",
>>> +                       freq_items[1].buf,
>>> +                       freq_items[0].buf);
>>> +
>>> +        lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>> +                       "%s%% RC6",
>>> +                       rc6_items[0].buf);
>>> +    } else {
>>> +        for (i = 0; i < engines->num_gts; i++) {
>>> +            const char *cont = !i ? " - ": "; ";
>>> +
>>> +            lines = print_header_token(cont, lines, con_w, con_h, &rem,
>>> +                           "%s/%s MHz(gt%d)",
>>> +                           freq_items_gt[i * 4 + 1].buf,
>>> +                           freq_items_gt[i * 4 + 0].buf,
>>> +                           i);
>>> +
>>> +            lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>> +                           "%s%% RC6(gt%d)",
>>> +                           rc6_items_gt[i * 3].buf,
>>> +                           i);
>>> +        }
>>> +    }
>>>      if (engines->r_gpu.present) {
>>>          lines = print_header_token("; ", lines, con_w, con_h,
>>
>> Series was a super easy read, thanks for that! Pretty much r-b for the 
>> lot from me but I would just like to visualize how the output looks 
>> like first. Would you mind pasting some examples for all the modes?
> 
> great, I am attaching the outputs in text files for MTL and DG2 here, 
> hope that is visible. If not, I can paste it in pastebin.
> 
> MTL shows the gt specific changes. DG2 is single tile, so there are no 
> changes.

Thank you, looks solid.

Only thing I would change is use uppercase GTn in the interactive 
output, so it matches with -l and -c.

Is it also doable to make the formatting of those labels match like "MHz 
GT0", or "GT0 MHz"?

Regards,

Tvrtko

Re: [igt-dev] [PATCH i-g-t 15/15] intel_gpu_top: Add gt specific values to header in interactive mode

[Umesh Nerlige Ramappa]

On Thu, May 11, 2023 at 08:50:58AM +0100, Tvrtko Ursulin wrote:
>
>On 10/05/2023 23:14, Umesh Nerlige Ramappa wrote:
>>On Wed, May 10, 2023 at 09:46:53AM +0100, Tvrtko Ursulin wrote:
>>>
>>>On 06/05/2023 01:55, Umesh Nerlige Ramappa wrote:
>>>>If -p options is specified in INTERACTIVE mode, show the gt specific
>>>>values.
>>>>
>>>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>>---
>>>> tools/intel_gpu_top.c | 33 +++++++++++++++++++++++++--------
>>>> 1 file changed, 25 insertions(+), 8 deletions(-)
>>>>
>>>>diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
>>>>index 0acc81e9e..7018499c7 100644
>>>>--- a/tools/intel_gpu_top.c
>>>>+++ b/tools/intel_gpu_top.c
>>>>@@ -1988,14 +1988,31 @@ print_header(const struct igt_device_card *card,
>>>>     lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
>>>>                    "%s", card->card);
>>>>-    lines = print_header_token(" - ", lines, con_w, con_h, &rem,
>>>>-                   "%s/%s MHz",
>>>>-                   freq_items[1].buf,
>>>>-                   freq_items[0].buf);
>>>>-
>>>>-    lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>>>-                   "%s%% RC6",
>>>>-                   rc6_items[0].buf);
>>>>+    if (class_view || engines->num_gts == 1) {
>>>>+        lines = print_header_token(" - ", lines, con_w, con_h, &rem,
>>>>+                       "%s/%s MHz",
>>>>+                       freq_items[1].buf,
>>>>+                       freq_items[0].buf);
>>>>+
>>>>+        lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>>>+                       "%s%% RC6",
>>>>+                       rc6_items[0].buf);
>>>>+    } else {
>>>>+        for (i = 0; i < engines->num_gts; i++) {
>>>>+            const char *cont = !i ? " - ": "; ";
>>>>+
>>>>+            lines = print_header_token(cont, lines, con_w, con_h, &rem,
>>>>+                           "%s/%s MHz(gt%d)",
>>>>+                           freq_items_gt[i * 4 + 1].buf,
>>>>+                           freq_items_gt[i * 4 + 0].buf,
>>>>+                           i);
>>>>+
>>>>+            lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>>>+                           "%s%% RC6(gt%d)",
>>>>+                           rc6_items_gt[i * 3].buf,
>>>>+                           i);
>>>>+        }
>>>>+    }
>>>>     if (engines->r_gpu.present) {
>>>>         lines = print_header_token("; ", lines, con_w, con_h,
>>>
>>>Series was a super easy read, thanks for that! Pretty much r-b for 
>>>the lot from me but I would just like to visualize how the output 
>>>looks like first. Would you mind pasting some examples for all the 
>>>modes?
>>
>>great, I am attaching the outputs in text files for MTL and DG2 
>>here, hope that is visible. If not, I can paste it in pastebin.
>>
>>MTL shows the gt specific changes. DG2 is single tile, so there are 
>>no changes.
>
>Thank you, looks solid.
>
>Only thing I would change is use uppercase GTn in the interactive 
>output, so it matches with -l and -c.
>
>Is it also doable to make the formatting of those labels match like 
>"MHz GT0", or "GT0 MHz"?

MHz GT0 looks good to me because that will keep the unit adjacent to the value. Something like this:

intel-gpu-top: Intel Meteorlake (Gen12) @ /dev/dri/card0 -      0/     0 MHz GT0;      100% RC6 GT0;      0/     0 MHz GT1;      100% RC6 GT1;  0.00/ 4.98 W;        0 irqs/s

Let me know if that's not what you meant.

Thanks,
Umesh


>
>Regards,
>
>Tvrtko

Re: [igt-dev] [PATCH i-g-t 15/15] intel_gpu_top: Add gt specific values to header in interactive mode

[Tvrtko Ursulin]

On 11/05/2023 19:08, Umesh Nerlige Ramappa wrote:
> On Thu, May 11, 2023 at 08:50:58AM +0100, Tvrtko Ursulin wrote:
>>
>> On 10/05/2023 23:14, Umesh Nerlige Ramappa wrote:
>>> On Wed, May 10, 2023 at 09:46:53AM +0100, Tvrtko Ursulin wrote:
>>>>
>>>> On 06/05/2023 01:55, Umesh Nerlige Ramappa wrote:
>>>>> If -p options is specified in INTERACTIVE mode, show the gt specific
>>>>> values.
>>>>>
>>>>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>>> ---
>>>>>  tools/intel_gpu_top.c | 33 +++++++++++++++++++++++++--------
>>>>>  1 file changed, 25 insertions(+), 8 deletions(-)
>>>>>
>>>>> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
>>>>> index 0acc81e9e..7018499c7 100644
>>>>> --- a/tools/intel_gpu_top.c
>>>>> +++ b/tools/intel_gpu_top.c
>>>>> @@ -1988,14 +1988,31 @@ print_header(const struct igt_device_card 
>>>>> *card,
>>>>>      lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
>>>>>                     "%s", card->card);
>>>>> -    lines = print_header_token(" - ", lines, con_w, con_h, &rem,
>>>>> -                   "%s/%s MHz",
>>>>> -                   freq_items[1].buf,
>>>>> -                   freq_items[0].buf);
>>>>> -
>>>>> -    lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>>>> -                   "%s%% RC6",
>>>>> -                   rc6_items[0].buf);
>>>>> +    if (class_view || engines->num_gts == 1) {
>>>>> +        lines = print_header_token(" - ", lines, con_w, con_h, &rem,
>>>>> +                       "%s/%s MHz",
>>>>> +                       freq_items[1].buf,
>>>>> +                       freq_items[0].buf);
>>>>> +
>>>>> +        lines = print_header_token("; ", lines, con_w, con_h, &rem,
>>>>> +                       "%s%% RC6",
>>>>> +                       rc6_items[0].buf);
>>>>> +    } else {
>>>>> +        for (i = 0; i < engines->num_gts; i++) {
>>>>> +            const char *cont = !i ? " - ": "; ";
>>>>> +
>>>>> +            lines = print_header_token(cont, lines, con_w, con_h, 
>>>>> &rem,
>>>>> +                           "%s/%s MHz(gt%d)",
>>>>> +                           freq_items_gt[i * 4 + 1].buf,
>>>>> +                           freq_items_gt[i * 4 + 0].buf,
>>>>> +                           i);
>>>>> +
>>>>> +            lines = print_header_token("; ", lines, con_w, con_h, 
>>>>> &rem,
>>>>> +                           "%s%% RC6(gt%d)",
>>>>> +                           rc6_items_gt[i * 3].buf,
>>>>> +                           i);
>>>>> +        }
>>>>> +    }
>>>>>      if (engines->r_gpu.present) {
>>>>>          lines = print_header_token("; ", lines, con_w, con_h,
>>>>
>>>> Series was a super easy read, thanks for that! Pretty much r-b for 
>>>> the lot from me but I would just like to visualize how the output 
>>>> looks like first. Would you mind pasting some examples for all the 
>>>> modes?
>>>
>>> great, I am attaching the outputs in text files for MTL and DG2 here, 
>>> hope that is visible. If not, I can paste it in pastebin.
>>>
>>> MTL shows the gt specific changes. DG2 is single tile, so there are 
>>> no changes.
>>
>> Thank you, looks solid.
>>
>> Only thing I would change is use uppercase GTn in the interactive 
>> output, so it matches with -l and -c.
>>
>> Is it also doable to make the formatting of those labels match like 
>> "MHz GT0", or "GT0 MHz"?
> 
> MHz GT0 looks good to me because that will keep the unit adjacent to the 
> value. Something like this:
> 
> intel-gpu-top: Intel Meteorlake (Gen12) @ /dev/dri/card0 -      0/     0 
> MHz GT0;      100% RC6 GT0;      0/     0 MHz GT1;      100% RC6 GT1;  
> 0.00/ 4.98 W;        0 irqs/s
> 
> Let me know if that's not what you meant.

Yes that looks better and is more consistent with the other output 
modes. It all looks good to me. For the series:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

[igt-dev] ✓ Fi.CI.BAT: success for PMU: multi-tile support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2640 bytes --]

== Series Details ==

Series: PMU: multi-tile support
URL   : https://patchwork.freedesktop.org/series/117406/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13115 -> IGTPW_8924
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/index.html

Participating hosts (40 -> 38)
------------------------------

  Missing    (2): bat-rpls-2 fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_8924 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg1-5:          [PASS][1] -> [ABORT][2] ([i915#4983])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/bat-dg1-5/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/bat-dg1-5/igt@i915_selftest@live@workarounds.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][3] ([fdo#109271])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/fi-bsw-n3050/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-bsw-n3050:       [ABORT][4] ([i915#7913]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/fi-bsw-n3050/igt@i915_selftest@live@execlists.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7281 -> IGTPW_8924

  CI-20190529: 20190529
  CI_DRM_13115: e0ccca9f289364f4e54b826c3f1feebbf121eaec @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8924: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/index.html
  IGT_7281: 9e9cd7e69a393b7cce8fc12fce409eb59817dd7e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@perf_pmu@rc6-all-gts
-igt@perf_pmu@frequency-idle
-igt@perf_pmu@rc6-runtime-pm
-igt@perf_pmu@rc6-runtime-pm-long

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/index.html

[-- Attachment #2: Type: text/html, Size: 3244 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for PMU: multi-tile support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 17458 bytes --]

== Series Details ==

Series: PMU: multi-tile support
URL   : https://patchwork.freedesktop.org/series/117406/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13115_full -> IGTPW_8924_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/index.html

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_8924_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@perf_pmu@frequency@gt0} (NEW):
    - {shard-dg1}:        NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-dg1-17/igt@perf_pmu@frequency@gt0.html

  * {igt@perf_pmu@rc6-all-gts} (NEW):
    - {shard-dg1}:        NOTRUN -> [SKIP][2] +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-dg1-16/igt@perf_pmu@rc6-all-gts.html
    - {shard-tglu}:       NOTRUN -> [SKIP][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-tglu-6/igt@perf_pmu@rc6-all-gts.html

  * {igt@perf_pmu@rc6@other-idle-gt0} (NEW):
    - {shard-rkl}:        NOTRUN -> [SKIP][4] +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-4/igt@perf_pmu@rc6@other-idle-gt0.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_mmap_offset@clear@smem0:
    - {shard-rkl}:        [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-2/igt@gem_mmap_offset@clear@smem0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-2/igt@gem_mmap_offset@clear@smem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - {shard-dg1}:        [PASS][7] -> [DMESG-WARN][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-dg1-14/igt@i915_module_load@reload-with-fault-injection.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-dg1-15/igt@i915_module_load@reload-with-fault-injection.html

  
New tests
---------

  New tests have been introduced between CI_DRM_13115_full and IGTPW_8924_full:

### New IGT tests (7) ###

  * igt@perf_pmu@frequency@gt0:
    - Statuses : 1 fail(s) 5 pass(s)
    - Exec time: [0.0] s

  * igt@perf_pmu@frequency@idle-gt0:
    - Statuses : 6 pass(s)
    - Exec time: [0.0] s

  * igt@perf_pmu@rc6-all-gts:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@perf_pmu@rc6@gt0:
    - Statuses : 6 pass(s)
    - Exec time: [0.0] s

  * igt@perf_pmu@rc6@other-idle-gt0:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@perf_pmu@rc6@runtime-pm-gt0:
    - Statuses : 5 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@perf_pmu@rc6@runtime-pm-long-gt0:
    - Statuses : 5 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_8924_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_barrier_race@remote-request@rcs0:
    - shard-apl:          [PASS][9] -> [ABORT][10] ([i915#7461] / [i915#8211] / [i915#8234])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-apl1/igt@gem_barrier_race@remote-request@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-apl4/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-glk1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-glk:          NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-glk9/igt@gem_lmem_swapping@parallel-random.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886]) +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-glk1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#2346])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          NOTRUN -> [FAIL][17] ([i915#2346])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-snb:          NOTRUN -> [SKIP][18] ([fdo#109271]) +40 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-snb2/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
    - shard-glk:          [PASS][19] -> [FAIL][20] ([i915#79])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-apl:          [PASS][21] -> [ABORT][22] ([i915#180])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-apl4/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
    - shard-glk:          NOTRUN -> [SKIP][23] ([fdo#109271]) +22 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-glk2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html

  * {igt@perf_pmu@rc6-all-gts} (NEW):
    - shard-apl:          NOTRUN -> [SKIP][24] ([fdo#109271]) +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-apl3/igt@perf_pmu@rc6-all-gts.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - {shard-rkl}:        [FAIL][25] ([i915#7742]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html

  * igt@gem_eio@hibernate:
    - {shard-tglu}:       [ABORT][27] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-tglu-10/igt@gem_eio@hibernate.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-tglu-4/igt@gem_eio@hibernate.html

  * igt@gem_exec_fair@basic-deadline:
    - {shard-rkl}:        [FAIL][29] ([i915#2846]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - {shard-rkl}:        [FAIL][31] ([i915#2842]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-4/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-glk:          [FAIL][33] ([i915#2842]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-glk9/igt@gem_exec_fair@basic-pace@vcs0.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-glk6/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@i915_pm_dc@dc9-dpms:
    - {shard-tglu}:       [SKIP][35] ([i915#4281]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-tglu-8/igt@i915_pm_dc@dc9-dpms.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - {shard-rkl}:        [SKIP][37] ([i915#1937]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rc6_residency@rc6-idle@bcs0:
    - {shard-dg1}:        [FAIL][39] ([i915#3591]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - {shard-rkl}:        [SKIP][41] ([i915#1397]) -> [PASS][42] +3 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_selftest@live@gt_pm:
    - {shard-rkl}:        [DMESG-FAIL][43] ([i915#4258]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-4/igt@i915_selftest@live@gt_pm.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-4/igt@i915_selftest@live@gt_pm.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [FAIL][45] ([i915#2346]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@single-move@pipe-b:
    - {shard-rkl}:        [INCOMPLETE][47] ([i915#8011]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-7/igt@kms_cursor_legacy@single-move@pipe-b.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-2/igt@kms_cursor_legacy@single-move@pipe-b.html

  * igt@perf_pmu@idle@rcs0:
    - {shard-dg1}:        [FAIL][49] ([i915#4349]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-dg1-16/igt@perf_pmu@idle@rcs0.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-dg1-16/igt@perf_pmu@idle@rcs0.html
    - {shard-rkl}:        [FAIL][51] ([i915#4349]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13115/shard-rkl-2/igt@perf_pmu@idle@rcs0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/shard-rkl-4/igt@perf_pmu@idle@rcs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
  [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7281 -> IGTPW_8924
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_13115: e0ccca9f289364f4e54b826c3f1feebbf121eaec @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8924: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/index.html
  IGT_7281: 9e9cd7e69a393b7cce8fc12fce409eb59817dd7e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8924/index.html

[-- Attachment #2: Type: text/html, Size: 15883 bytes --]

[igt-dev] [PATCH i-g-t 00/15] PMU: multi-tile support

[Umesh Nerlige Ramappa]

Enable IGT PMU support for multi-tile platforms.
Add multi-tile support for intel_gpu_top.

v2: (Tvrtko)
- Instead of adding gtN suffix to item, add it to parent group
- Show split gt values only if -p option is specified
- Display aggregate value as default without -p option
- Break down patches into reviewable units

v3: (Ashutosh, Tvrtko)
- Reformat GT info in INTERACTIVE mode
- Use i915_for_each_gt
- Move uapi to i915_drm_local.h
- Use gem_list_engines() and drop unnecessary code

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Riana Tauro (1):
  perf_pmu: Use correct pmu config for multi-tile

Tvrtko Ursulin (3):
  perf_pmu: Support multi-tile in rc6 subtest
  perf_pmu: Two new rc6 subtests
  perf_pmu: Support multi-tile in frequency subtest

Umesh Nerlige Ramappa (11):
  perf_pmu: Quiesce GPU if measuring idle busyness without spinner
  intel_gpu_top: Add an array of freq and rc6 counters
  intel_gpu_top: Determine number of tiles
  intel_gpu_top: Capture freq and rc6 counters from each gt
  intel_gpu_top: Switch pmu_counter to use aggregated values
  intel_gpu_top: Add definitions for gt-specific items and groups
  intel_gpu_top: Bump up size of groups to accomodate multi-gt
  intel_gpu_top: Increase visibility for class_view
  intel_gpu_top: Show gt specific values if requested
  intel_gpu_top: Reduce one level of indent
  intel_gpu_top: Add gt specific values to header in interactive mode

 lib/i915/i915_drm_local.h |  15 ++
 tests/i915/perf_pmu.c     | 307 +++++++++++++++++++++++++++-----------
 tools/intel_gpu_top.c     | 238 ++++++++++++++++++++++++-----
 3 files changed, 432 insertions(+), 128 deletions(-)

-- 
2.36.1

[igt-dev] [PATCH i-g-t 04/15] perf_pmu: Quiesce GPU if measuring idle busyness without spinner

[Umesh Nerlige Ramappa]

The assumption in some tests is that the engines are not busy if no
spinners are being run. This is not true in some cases where we see
that the render is busy at the start of the test. Quiesce GPU to wait
for such work to complete before checking for idle busyness.

v2: Move gem_quiescent_gpu to beginning of test (Tvrtko)

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/i915/perf_pmu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 155fc5f48..38bdee650 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -279,6 +279,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
 	int fd;
 	uint64_t ahnd = get_reloc_ahnd(gem_fd, ctx->id);
 
+	gem_quiescent_gpu(gem_fd);
 	fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
 	if (flags & TEST_BUSY)
@@ -639,6 +640,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
 	int fd[2];
 	uint64_t ahnd = get_reloc_ahnd(gem_fd, ctx->id);
 
+	gem_quiescent_gpu(gem_fd);
 	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
 			   -1);
 	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance),
-- 
2.36.1