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bh=CFw+yTcp8Rs5oYiyy6E/8TnY6ckX3xkbIRUe1/913pw=; b=abdov31J3JFWKXd7bcXVZ30cPaU1cwI54kSM0UH78mVjgasqOvA5iQaGW4+ebSjkLEPL1r 2lGYzchTnpJ4+FhAljSBE2foBetqXpzFSoCa0TwegVgVGj4+mNHHZG4ee5UM3VN2lVuvQJ VRhsZ2XG4oElBccukuPQ3mIt1j3kzj8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-189-kBEjZOoAPEiISqMB9AZkSw-1; Wed, 16 Jun 2021 05:46:27 -0400 X-MC-Unique: kBEjZOoAPEiISqMB9AZkSw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 44057C73AA; Wed, 16 Jun 2021 09:46:26 +0000 (UTC) Received: from localhost (ovpn-113-141.ams2.redhat.com [10.36.113.141]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9D51C5C1C5; Wed, 16 Jun 2021 09:46:18 +0000 (UTC) From: Cornelia Huck To: Eric Farman , qemu-devel@nongnu.org, qemu-s390x@nongnu.org Subject: Re: [PATCH v3 1/4] s390x/css: Introduce an ESW struct In-Reply-To: <20210616014749.2460133-2-farman@linux.ibm.com> Organization: Red Hat GmbH References: <20210616014749.2460133-1-farman@linux.ibm.com> <20210616014749.2460133-2-farman@linux.ibm.com> User-Agent: Notmuch/0.32.1 (https://notmuchmail.org) Date: Wed, 16 Jun 2021 11:46:17 +0200 Message-ID: <87r1h2w39y.fsf@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=cohuck@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=216.205.24.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.197, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Matthew Rosato , David Hildenbrand , Richard Henderson , Eric Farman , Halil Pasic , Christian Borntraeger , Alex Williamson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Jun 16 2021, Eric Farman wrote: > The Interrupt Response Block is comprised of several other > structures concatenated together, but only the 12-byte > Subchannel-Status Word (SCSW) is defined as a proper struct. > Everything else is a simple array of 32-bit words. > > Let's define a proper struct for the 20-byte Extended-Status > Word (ESW) so that we can make good decisions about the sense > data that would go into the ECW area for virtual vs > passthrough devices. > > Signed-off-by: Eric Farman > --- > hw/s390x/css.c | 19 +++++++++++++------ > include/hw/s390x/ioinst.h | 12 +++++++++++- > 2 files changed, 24 insertions(+), 7 deletions(-) > (...) > diff --git a/include/hw/s390x/ioinst.h b/include/hw/s390x/ioinst.h > index c6737a30d4..9613e0ccbb 100644 > --- a/include/hw/s390x/ioinst.h > +++ b/include/hw/s390x/ioinst.h > @@ -123,10 +123,20 @@ typedef struct SCHIB { > uint8_t mda[4]; > } QEMU_PACKED SCHIB; > > +/* extended-status word */ > +typedef struct ESW { > + uint32_t sublog; > + uint32_t erw; > + uint64_t f_addr; > + uint32_t s_addr; > +} QEMU_PACKED ESW; Strictly speaking, that's a format 0 esw. Doesn't matter too much in the end, I think: - erw is always the same - f_addr and s_addr are always 0 for the other formats - 'sublog' is always a u32 with the lpum in the same place (which we always set to 0x80 for virtual subchannels, as they have only one path) > + > +#define ESW_ERW_SENSE 0x01000000 > + > /* interruption response block */ > typedef struct IRB { > SCSW scsw; > - uint32_t esw[5]; > + ESW esw; > uint32_t ecw[8]; > uint32_t emw[8]; > } IRB;