From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89B1FC43215 for ; Tue, 3 Dec 2019 12:41:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 680E02068E for ; Tue, 3 Dec 2019 12:41:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 680E02068E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DDEF26E4AB; Tue, 3 Dec 2019 12:41:08 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id DF4646E4AB; Tue, 3 Dec 2019 12:41:07 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Dec 2019 04:41:07 -0800 X-IronPort-AV: E=Sophos;i="5.69,273,1571727600"; d="scan'208";a="204962080" Received: from jnikula-mobl3.fi.intel.com (HELO localhost) ([10.237.66.161]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Dec 2019 04:41:03 -0800 From: Jani Nikula To: Lyude Paul , intel-gfx@lists.freedesktop.org Subject: Re: [PATCH 3/5] drm/i915: Fix DPCD register order in intel_dp_aux_enable_backlight() In-Reply-To: <20191122231616.2574-4-lyude@redhat.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20191122231616.2574-1-lyude@redhat.com> <20191122231616.2574-4-lyude@redhat.com> Date: Tue, 03 Dec 2019 14:41:00 +0200 Message-ID: <87r21lintv.fsf@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rodrigo Vivi , Lee Shawn C Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" T24gRnJpLCAyMiBOb3YgMjAxOSwgTHl1ZGUgUGF1bCA8bHl1ZGVAcmVkaGF0LmNvbT4gd3JvdGU6 Cj4gRm9yIGVEUCBwYW5lbHMsIGl0IGFwcGVhcnMgaXQncyBleHBlY3RlZCB0aGF0IHNvIGxvbmcg YXMgdGhlIHBhbmVsIGlzIGluCj4gRFBDRCBjb250cm9sIG1vZGUgdGhhdCB0aGUgYnJpZ2h0bmVz cyB2YWx1ZSBpcyBuZXZlciBzZXQgdG8gMC4gSW5zdGVhZCwKPiBpZiB0aGUgZGVzaXJlZCBlZmZl Y3QgaXMgdG8gc2V0IHRoZSBwYW5lbCdzIGJhY2tsaWdodCB0byAwIHdlJ3JlCj4gZXhwZWN0ZWQg dG8gc2ltcGx5IHR1cm4gb2ZmIHRoZSBiYWNrbGlnaHQgdGhyb3VnaCB0aGUKPiBEUF9FRFBfRElT UExBWV9DT05UUk9MX1JFR0lTVEVSLgo+Cj4gV2UgYWxyZWFkeSBkbyB0aGUgbGF0dGVyIGNvcnJl Y3RseSBpbiBpbnRlbF9kcF9hdXhfZGlzYWJsZV9iYWNrbGlnaHQoKS4KPiBCdXQsIHdlIG1ha2Ug dGhlIG1pc3Rha2Ugb2Ygd3JpdGluZyB0aGUgRFBDRCByZWdpc3RlcnMgaW4gdGhlIHdyb25nCj4g b3JkZXIgd2hlbiBlbmFibGluZyB0aGUgYmFja2xpZ2h0IGluIGludGVsX2RwX2F1eF9lbmFibGVf YmFja2xpZ2h0KCkKPiBzaW5jZSB3ZSBjdXJyZW50bHkgZW5hYmxlIHRoZSBiYWNrbGlnaHQgdGhy b3VnaAo+IERQX0VEUF9ESVNQTEFZX0NPTlRST0xfUkVHSVNURVIgYmVmb3JlIHdyaXRpbmcgdGhl IGJyaWdodG5lc3MgbGV2ZWwuIE9uCj4gdGhlIFgxIEV4dHJlbWUgMm5kIEdlbmVyYXRpb24sIHRo aXMgYXBwZWFycyB0byBoYXZlIHRoZSBwb3RlbnRpYWwgb2YKPiBjb25mdXNpbmcgdGhlIHBhbmVs IGluIHN1Y2ggYSB3YXkgdGhhdCBmdXJ0aGVyIGF0dGVtcHRzIHRvIHNldCB0aGUKPiBicmlnaHRu ZXNzIGRvbid0IGFjdHVhbGx5IGNoYW5nZSB0aGUgYmFja2xpZ2h0IGFzIGV4cGVjdGVkIGFuZCBs ZWF2ZSBpdAo+IG9mZi4gUHJlc3VtYWJseSwgdGhpcyBoYXBwZW5zIGJlY2F1c2UgdGhlIGluY29y cmVjdCByZWdpc3RlciB3cml0aW5nCj4gb3JkZXIgYnJpZWZseSBsZWF2ZXMgdGhlIHBhbmVsIHdp dGggRFBDRCBtb2RlIGVuYWJsZWQgYW5kIGEgMCBicmlnaHRuZXNzCj4gbGV2ZWwgc2V0Lgo+Cj4g U28sIHJldmVyc2UgdGhlIG9yZGVyIHdlIHdyaXRlIHRoZSBEUENEIHJlZ2lzdGVycyB3aGVuIGVu YWJsaW5nIHRoZQo+IHBhbmVsIGJhY2tsaWdodCBzbyB0aGF0IHdlIHdyaXRlIHRoZSBicmlnaHRu ZXNzIHZhbHVlIGZpcnN0LCBhbmQgZW5hYmxlCj4gdGhlIGJhY2tsaWdodCBzZWNvbmQuIFRoaXMg Zml4IGFwcGVhcnMgdG8gYmUgdGhlIGZpbmFsIGJpdCBuZWVkZWQgdG8gZ2V0Cj4gdGhlIGJhY2ts aWdodCBvbiB0aGUgVGhpbmtQYWQgWDEgRXh0cmVtZSAybmQgR2VuZXJhdGlvbidzIEFNT0xFRCBz Y3JlZW4KPiB3b3JraW5nLgo+Cj4gU2lnbmVkLW9mZi1ieTogTHl1ZGUgUGF1bCA8bHl1ZGVAcmVk aGF0LmNvbT4KClJldmlld2VkLWJ5OiBKYW5pIE5pa3VsYSA8amFuaS5uaWt1bGFAaW50ZWwuY29t PgoKPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcF9hdXhfYmFj a2xpZ2h0LmMgfCAzICsrLQo+ICAxIGZpbGUgY2hhbmdlZCwgMiBpbnNlcnRpb25zKCspLCAxIGRl bGV0aW9uKC0pCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9p bnRlbF9kcF9hdXhfYmFja2xpZ2h0LmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9kaXNwbGF5L2lu dGVsX2RwX2F1eF9iYWNrbGlnaHQuYwo+IGluZGV4IDBiZjg3NzJiYzdiYi4uODdiNTlkYjlmZmUz IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHBfYXV4 X2JhY2tsaWdodC5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9k cF9hdXhfYmFja2xpZ2h0LmMKPiBAQCAtMjA1LDggKzIwNSw5IEBAIHN0YXRpYyB2b2lkIGludGVs X2RwX2F1eF9lbmFibGVfYmFja2xpZ2h0KGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpj cnRjX3N0Cj4gIAkJfQo+ICAJfQo+ICAKPiArCWludGVsX2RwX2F1eF9zZXRfYmFja2xpZ2h0KGNv bm5fc3RhdGUsCj4gKwkJCQkgICBjb25uZWN0b3ItPnBhbmVsLmJhY2tsaWdodC5sZXZlbCk7Cj4g IAlzZXRfYXV4X2JhY2tsaWdodF9lbmFibGUoaW50ZWxfZHAsIHRydWUpOwo+IC0JaW50ZWxfZHBf YXV4X3NldF9iYWNrbGlnaHQoY29ubl9zdGF0ZSwgY29ubmVjdG9yLT5wYW5lbC5iYWNrbGlnaHQu bGV2ZWwpOwo+ICB9Cj4gIAo+ICBzdGF0aWMgdm9pZCBpbnRlbF9kcF9hdXhfZGlzYWJsZV9iYWNr bGlnaHQoY29uc3Qgc3RydWN0IGRybV9jb25uZWN0b3Jfc3RhdGUgKm9sZF9jb25uX3N0YXRlKQoK LS0gCkphbmkgTmlrdWxhLCBJbnRlbCBPcGVuIFNvdXJjZSBHcmFwaGljcyBDZW50ZXIKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxp bmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJl ZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVs From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 308F9C432C3 for ; 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03 Dec 2019 04:41:07 -0800 X-IronPort-AV: E=Sophos;i="5.69,273,1571727600"; d="scan'208";a="204962080" Received: from jnikula-mobl3.fi.intel.com (HELO localhost) ([10.237.66.161]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Dec 2019 04:41:03 -0800 From: Jani Nikula To: Lyude Paul , intel-gfx@lists.freedesktop.org In-Reply-To: <20191122231616.2574-4-lyude@redhat.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20191122231616.2574-1-lyude@redhat.com> <20191122231616.2574-4-lyude@redhat.com> Date: Tue, 03 Dec 2019 14:41:00 +0200 Message-ID: <87r21lintv.fsf@intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH 3/5] drm/i915: Fix DPCD register order in intel_dp_aux_enable_backlight() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Content-Type: text/plain; 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Tue, 3 Dec 2019 12:41:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 275E720684 for ; Tue, 3 Dec 2019 12:41:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726224AbfLCMlH (ORCPT ); Tue, 3 Dec 2019 07:41:07 -0500 Received: from mga03.intel.com ([134.134.136.65]:17530 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725997AbfLCMlH (ORCPT ); Tue, 3 Dec 2019 07:41:07 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Dec 2019 04:41:07 -0800 X-IronPort-AV: E=Sophos;i="5.69,273,1571727600"; d="scan'208";a="204962080" Received: from jnikula-mobl3.fi.intel.com (HELO localhost) ([10.237.66.161]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Dec 2019 04:41:03 -0800 From: Jani Nikula To: Lyude Paul , intel-gfx@lists.freedesktop.org Cc: Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Chris Wilson , Maarten Lankhorst , Lee Shawn C , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/5] drm/i915: Fix DPCD register order in intel_dp_aux_enable_backlight() In-Reply-To: <20191122231616.2574-4-lyude@redhat.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20191122231616.2574-1-lyude@redhat.com> <20191122231616.2574-4-lyude@redhat.com> Date: Tue, 03 Dec 2019 14:41:00 +0200 Message-ID: <87r21lintv.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 22 Nov 2019, Lyude Paul wrote: > For eDP panels, it appears it's expected that so long as the panel is in > DPCD control mode that the brightness value is never set to 0. Instead, > if the desired effect is to set the panel's backlight to 0 we're > expected to simply turn off the backlight through the > DP_EDP_DISPLAY_CONTROL_REGISTER. > > We already do the latter correctly in intel_dp_aux_disable_backlight(). > But, we make the mistake of writing the DPCD registers in the wrong > order when enabling the backlight in intel_dp_aux_enable_backlight() > since we currently enable the backlight through > DP_EDP_DISPLAY_CONTROL_REGISTER before writing the brightness level. On > the X1 Extreme 2nd Generation, this appears to have the potential of > confusing the panel in such a way that further attempts to set the > brightness don't actually change the backlight as expected and leave it > off. Presumably, this happens because the incorrect register writing > order briefly leaves the panel with DPCD mode enabled and a 0 brightness > level set. > > So, reverse the order we write the DPCD registers when enabling the > panel backlight so that we write the brightness value first, and enable > the backlight second. This fix appears to be the final bit needed to get > the backlight on the ThinkPad X1 Extreme 2nd Generation's AMOLED screen > working. > > Signed-off-by: Lyude Paul Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > index 0bf8772bc7bb..87b59db9ffe3 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > @@ -205,8 +205,9 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st > } > } > > + intel_dp_aux_set_backlight(conn_state, > + connector->panel.backlight.level); > set_aux_backlight_enable(intel_dp, true); > - intel_dp_aux_set_backlight(conn_state, connector->panel.backlight.level); > } > > static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old_conn_state) -- Jani Nikula, Intel Open Source Graphics Center