diff for duplicates of <87r2w34pab.fsf@linaro.org> diff --git a/a/1.txt b/N1/1.txt index c9d6961..d87d517 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -88,3 +88,7 @@ Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > mov x0, #1 << 12 // Reset mdscr_el1 and disable > msr mdscr_el1, x0 // access to the DCC from EL0 > isb // Unmask debug exceptions now, + + +-- +Alex Bennée diff --git a/a/content_digest b/N1/content_digest index b95be57..0674d32 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -104,6 +104,10 @@ "> +\n" "> \tmov\tx0, #1 << 12\t\t\t// Reset mdscr_el1 and disable\n" "> \tmsr\tmdscr_el1, x0\t\t\t// access to the DCC from EL0\n" - "> \tisb\t\t\t\t\t// Unmask debug exceptions now," + "> \tisb\t\t\t\t\t// Unmask debug exceptions now,\n" + "\n" + "\n" + "--\n" + "Alex Benn\303\251e" -d6c77ce3ee8b2337952174f8269bf401565b341eea2e3351303ef3d66a64964a +22f602e22f951de90c795c87dbc732846163c555eab165d4646c249ef2e4630b
diff --git a/a/1.txt b/N2/1.txt index c9d6961..513c574 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -45,7 +45,7 @@ Especially as the second one needs an isb :-/ But I don't see a much neater way of doing it so: -Reviewed-by: Alex Bennée <alex.bennee@linaro.org> +Reviewed-by: Alex Benn?e <alex.bennee@linaro.org> > + mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector > + msr_s SYS_ZCR_EL2, x1 // length for EL1. @@ -88,3 +88,7 @@ Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > mov x0, #1 << 12 // Reset mdscr_el1 and disable > msr mdscr_el1, x0 // access to the DCC from EL0 > isb // Unmask debug exceptions now, + + +-- +Alex Benn?e diff --git a/a/content_digest b/N2/content_digest index b95be57..79ea1b5 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,18 +1,9 @@ "ref\01502280338-23002-1-git-send-email-Dave.Martin@arm.com\0" "ref\01502280338-23002-11-git-send-email-Dave.Martin@arm.com\0" - "From\0Alex Benn\303\251e <alex.bennee@linaro.org>\0" - "Subject\0Re: [PATCH 10/27] arm64/sve: Low-level CPU setup\0" + "From\0alex.bennee@linaro.org (Alex Benn\303\251e)\0" + "Subject\0[PATCH 10/27] arm64/sve: Low-level CPU setup\0" "Date\0Tue, 22 Aug 2017 16:04:28 +0100\0" - "To\0Dave Martin <Dave.Martin@arm.com>\0" - "Cc\0linux-arm-kernel@lists.infradead.org" - linux-arch@vger.kernel.org - libc-alpha@sourceware.org - Ard Biesheuvel <ard.biesheuvel@linaro.org> - Szabolcs Nagy <szabolcs.nagy@arm.com> - Catalin Marinas <catalin.marinas@arm.com> - Will Deacon <will.deacon@arm.com> - Richard Sandiford <richard.sandiford@arm.com> - " kvmarm@lists.cs.columbia.edu\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" @@ -62,7 +53,7 @@ "\n" "But I don't see a much neater way of doing it so:\n" "\n" - "Reviewed-by: Alex Benn\303\251e <alex.bennee@linaro.org>\n" + "Reviewed-by: Alex Benn?e <alex.bennee@linaro.org>\n" "\n" "> +\tmov\tx1, #ZCR_ELx_LEN_MASK\t\t// SVE: Enable full vector\n" "> +\tmsr_s\tSYS_ZCR_EL2, x1\t\t\t// length for EL1.\n" @@ -104,6 +95,10 @@ "> +\n" "> \tmov\tx0, #1 << 12\t\t\t// Reset mdscr_el1 and disable\n" "> \tmsr\tmdscr_el1, x0\t\t\t// access to the DCC from EL0\n" - "> \tisb\t\t\t\t\t// Unmask debug exceptions now," + "> \tisb\t\t\t\t\t// Unmask debug exceptions now,\n" + "\n" + "\n" + "--\n" + Alex Benn?e -d6c77ce3ee8b2337952174f8269bf401565b341eea2e3351303ef3d66a64964a +b6b9fd3fe879a65de71991a4e08c4cd45b0eede9bedc6e1912b517c4575be626
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