From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH 7/7] drm/i915: Stop RPS as we adjust thresholds Date: Mon, 20 Feb 2017 16:41:47 +0200 Message-ID: <87r32sdivo.fsf@gaia.fi.intel.com> References: <20170220094713.22874-1-chris@chris-wilson.co.uk> <20170220094713.22874-7-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id C4A986E417 for ; Mon, 20 Feb 2017 14:42:58 +0000 (UTC) In-Reply-To: <20170220094713.22874-7-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org Q2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13aWxzb24uY28udWs+IHdyaXRlczoKCj4gRGlzYWJs ZSBSUFMgYnkgc2V0dGluZyBSUF9DT05UUk9MIHRvIDAsIHJlbWVtYmVyaW5nIGl0cyBlYXJsaWVy IHZhbHVlLgo+IFRoZW4gYWRqdXN0IHRoZSB0aHJlc2hvbGRzIGJlZm9yZSByZS1lbmFibGluZyBS UF9DT05UUk9MLgo+Cj4gU2lnbmVkLW9mZi1ieTogQ2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13 aWxzb24uY28udWs+Cj4gQ2M6IE1pa2EgS3VvcHBhbGEgPG1pa2Eua3VvcHBhbGFAbGludXguaW50 ZWwuY29tPgo+IENjOiBzdGFibGVAdmdlci5rZXJuZWwub3JnCgpSZXZpZXdlZC1ieTogTWlrYSBL dW9wcGFsYSA8bWlrYS5rdW9wcGFsYUBpbnRlbC5jb20+Cgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9k cm0vaTkxNS9pbnRlbF9wbS5jIHwgMTAgKysrKysrKystLQo+ICAxIGZpbGUgY2hhbmdlZCwgOCBp bnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKQo+Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1 L2RybS9pOTE1L2ludGVsX3BtLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wbS5jCj4g aW5kZXggZDM3ZTk1YjM1MjVkLi5lNWNmYTAzNzczNjcgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9n cHUvZHJtL2k5MTUvaW50ZWxfcG0uYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVs X3BtLmMKPiBAQCAtNDgwNCw2ICs0ODA0LDcgQEAgc3RhdGljIHZvaWQgZ2VuNl9zZXRfcnBzX3Ro cmVzaG9sZHMoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LCB1OCB2YWwpCj4gIAlp bnQgbmV3X3Bvd2VyOwo+ICAJdTMyIHRocmVzaG9sZF91cCA9IDAsIHRocmVzaG9sZF9kb3duID0g MDsgLyogaW4gJSAqLwo+ICAJdTMyIGVpX3VwID0gMCwgZWlfZG93biA9IDA7Cj4gKwl1MzIgcnBf Y29udHJvbDsKPiAgCj4gIAluZXdfcG93ZXIgPSBkZXZfcHJpdi0+cnBzLnBvd2VyOwo+ICAJc3dp dGNoIChkZXZfcHJpdi0+cnBzLnBvd2VyKSB7Cj4gQEAgLTQ4NzIsNiArNDg3MywxMiBAQCBzdGF0 aWMgdm9pZCBnZW42X3NldF9ycHNfdGhyZXNob2xkcyhzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAq ZGV2X3ByaXYsIHU4IHZhbCkKPiAgCXNwaW5fbG9ja19pcnEoJmRldl9wcml2LT51bmNvcmUubG9j ayk7Cj4gIAlpbnRlbF91bmNvcmVfZm9yY2V3YWtlX2dldF9fbG9ja2VkKGRldl9wcml2LCBGT1JD RVdBS0VfQUxMKTsKPiAgCj4gKwkvKiBTdG9wIFJQUyBiZWZvcmUgY2hhbmdpbmcgdGhyZXNob2xk cyAqLwo+ICsJcnBfY29udHJvbCA9IEk5MTVfUkVBRF9GVyhHRU42X1JQX0NPTlRST0wpOwo+ICsJ STkxNV9XUklURV9GVyhHRU42X1JQX0NPTlRST0wsIDApOwo+ICsJUE9TVElOR19SRUFEX0ZXKEdF TjZfUlBfQ09OVFJPTCk7Cj4gKwo+ICsJLyogVXBkYXRlIHRocmVzaG9sZHMgYW5kIGV2YWx1YXRp b24gaW50ZXJ2YWxzICovCj4gIAlJOTE1X1dSSVRFX0ZXKEdFTjZfUlBfVVBfRUksCj4gIAkJICAg ICAgR1RfSU5URVJWQUxfRlJPTV9VUyhkZXZfcHJpdiwgZWlfdXApKTsKPiAgCUk5MTVfV1JJVEVf RlcoR0VONl9SUF9VUF9USFJFU0hPTEQsCj4gQEAgLTQ4ODUsOCArNDg5Miw3IEBAIHN0YXRpYyB2 b2lkIGdlbjZfc2V0X3Jwc190aHJlc2hvbGRzKHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZf cHJpdiwgdTggdmFsKQo+ICAJCQkJCSAgZWlfZG93biAqIHRocmVzaG9sZF9kb3duIC8gMTAwKSk7 Cj4gIAo+ICAJLyogUmVzdGFydCBSUFMgdG8gcmVsb2FkIHRoZSB0aHJlc2hvbGRzICovCj4gLQlJ OTE1X1dSSVRFX0ZXKEdFTjZfUlBfQ09OVFJPTCwKPiAtCQkgICAgICBJOTE1X1JFQURfRlcoR0VO Nl9SUF9DT05UUk9MKSB8IEdFTjZfUlBfRU5BQkxFKTsKPiArCUk5MTVfV1JJVEVfRlcoR0VONl9S UF9DT05UUk9MLCBycF9jb250cm9sIHwgR0VONl9SUF9FTkFCTEUpOwo+ICAKPiAgCWludGVsX3Vu Y29yZV9mb3JjZXdha2VfcHV0X19sb2NrZWQoZGV2X3ByaXYsIEZPUkNFV0FLRV9BTEwpOwo+ICAJ c3Bpbl91bmxvY2tfaXJxKCZkZXZfcHJpdi0+dW5jb3JlLmxvY2spOwo+IC0tIAo+IDIuMTEuMApf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZngg bWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com ([192.55.52.88]:48070 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752767AbdBTOnJ (ORCPT ); Mon, 20 Feb 2017 09:43:09 -0500 From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Chris Wilson , stable@vger.kernel.org Subject: Re: [PATCH 7/7] drm/i915: Stop RPS as we adjust thresholds In-Reply-To: <20170220094713.22874-7-chris@chris-wilson.co.uk> References: <20170220094713.22874-1-chris@chris-wilson.co.uk> <20170220094713.22874-7-chris@chris-wilson.co.uk> Date: Mon, 20 Feb 2017 16:41:47 +0200 Message-ID: <87r32sdivo.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: Chris Wilson writes: > Disable RPS by setting RP_CONTROL to 0, remembering its earlier value. > Then adjust the thresholds before re-enabling RP_CONTROL. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: stable@vger.kernel.org Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index d37e95b3525d..e5cfa0377367 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4804,6 +4804,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > int new_power; > u32 threshold_up = 0, threshold_down = 0; /* in % */ > u32 ei_up = 0, ei_down = 0; > + u32 rp_control; > > new_power = dev_priv->rps.power; > switch (dev_priv->rps.power) { > @@ -4872,6 +4873,12 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > spin_lock_irq(&dev_priv->uncore.lock); > intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); > > + /* Stop RPS before changing thresholds */ > + rp_control = I915_READ_FW(GEN6_RP_CONTROL); > + I915_WRITE_FW(GEN6_RP_CONTROL, 0); > + POSTING_READ_FW(GEN6_RP_CONTROL); > + > + /* Update thresholds and evaluation intervals */ > I915_WRITE_FW(GEN6_RP_UP_EI, > GT_INTERVAL_FROM_US(dev_priv, ei_up)); > I915_WRITE_FW(GEN6_RP_UP_THRESHOLD, > @@ -4885,8 +4892,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > ei_down * threshold_down / 100)); > > /* Restart RPS to reload the thresholds */ > - I915_WRITE_FW(GEN6_RP_CONTROL, > - I915_READ_FW(GEN6_RP_CONTROL) | GEN6_RP_ENABLE); > + I915_WRITE_FW(GEN6_RP_CONTROL, rp_control | GEN6_RP_ENABLE); > > intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); > spin_unlock_irq(&dev_priv->uncore.lock); > -- > 2.11.0