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Thu, 21 May 2026 10:50:59 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4903caede9fsm43911755e9.14.2026.05.21.10.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 10:50:58 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 9578A5F886; Thu, 21 May 2026 18:50:57 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: Re: [PATCH 2/3] target/arm: Use FPST_A64_F16 for SVE FCVTLT_hs In-Reply-To: (Peter Maydell's message of "Thu, 21 May 2026 16:21:19 +0100") References: <20260521122913.1565011-1-peter.maydell@linaro.org> <20260521122913.1565011-3-peter.maydell@linaro.org> <87mrxsolqb.fsf@draig.linaro.org> User-Agent: mu4e 1.14.1; emacs 30.1 Date: Thu, 21 May 2026 18:50:57 +0100 Message-ID: <87se7kmz26.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Peter Maydell writes: > On Thu, 21 May 2026 at 15:55, Alex Benn=C3=A9e w= rote: >> >> Peter Maydell writes: >> >> > The SVE FCVTLT_hs operation produces a halfprec result, so we should >> > use the FPST_A64_F16 fpstatus for it. >> >> Maybe I'm reading the Arm ARM wrong (I can't find FCVTLT_hs but I can >> see FCVTLT in the SVE encodings). But these are all widening operations >> so I can see halfprec to single, not the other way around. > > Yes, I got the commit message wrong here; this is half to single, > and we need to use the A64_F16 fpstatus for conversions from > halfprec, not conversions to it. The e07b48995aaa commit message > does a better job of explaining this than I did this time around. > > The _hs is how the QEMU decode file splits the half to single > and the single to double encodings, which are the same insn > mnememonic in the architecture. > > Improved commit message: > > =3D=3D=3Dbegin=3D=3D=3D > We should be using the F16-specific float_status for conversions from > half-precision, because halfprec inputs never set Input Denormal. > If we use the FPST_A64 fpstatus then we will incorrectly set > FPCR.IDC for input-denormals when FPCR.AH=3D1. > > In commit e07b48995aaa we updated most of the halfprec-to-other > conversion insns to use FPST_A64_F16 as part of implementing FEAT_AHP. > However we missed the SVE FCVTLT instruction, which has a > halfprec-to-single encoding. > > Correct the FPST we use for the hs variant of FCVTLT. > > [cc, fixes, &c] > =3D=3D=3Dendit=3D=3D=3D > Reviewed-by: Alex Benn=C3=A9e > > thanks > -- PMM --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro