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Thu, 05 Feb 2026 12:57:30 -0800 (PST) Received: from draig.lan ([185.124.0.126]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacb18d0sm18538166b.40.2026.02.05.12.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Feb 2026 12:57:30 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 27C635F8BF; Thu, 05 Feb 2026 20:57:29 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Mohamed Mediouni Cc: Richard Henderson , qemu-devel@nongnu.org Subject: Re: [PATCH v2] target/arm: implement FEAT_E2H0 In-Reply-To: <10F9A8B0-27FD-40B3-9299-E27883823423@unpredictable.fr> (Mohamed Mediouni's message of "Thu, 5 Feb 2026 14:02:26 +0100") References: <20260204131353.2977855-1-alex.bennee@linaro.org> <3e6ab807-37df-40ba-840e-4693071691f7@linaro.org> <877bsrnzvd.fsf@draig.linaro.org> <10F9A8B0-27FD-40B3-9299-E27883823423@unpredictable.fr> User-Agent: mu4e 1.14.0-pre1; emacs 30.1 Date: Thu, 05 Feb 2026 20:57:29 +0000 Message-ID: <87sebenc1y.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Mohamed Mediouni writes: >> On 5. Feb 2026, at 13:23, Alex Benn=C3=A9e wrot= e: >>=20 >> Richard Henderson writes: >>=20 >>> On 2/4/26 23:13, Alex Benn=C3=A9e wrote: >>>> FEAT_E2H0 is a formalisation of the existing behaviour of HCR_EL2.E2H >>>> being programmable to switch between EL2 host mode and the >>>> "traditional" nVHE EL2 mode. This implies at some point we might want >>>> to model CPUs without FEAT_E2H0 which will always have EL2 host mode >>>> enabled. >>>> There are two values to represent no E2H0 systems of which 0b1110 >>>> will >>>> make HCR_EL2.NV1 RES0 for FEAT_NV systems. For FEAT_NV2 the NV1 bit is >>>> always valid. >>>> Message-ID: <20260130181648.628364-1-alex.bennee@linaro.org> >>>> Signed-off-by: Alex Benn=C3=A9e >>>> --- >>>> v2 >>>> - new helper and properly handling NV1 >>>> --- >> >>>=20 >>>> @@ -3801,10 +3802,13 @@ static void do_hcr_write(CPUARMState *env, uin= t64_t value, uint64_t valid_mask) >>>> valid_mask |=3D HCR_GPF; >>>> } >>>> if (cpu_isar_feature(aa64_nv, cpu)) { >>>> - valid_mask |=3D HCR_NV | HCR_NV1 | HCR_AT; >>>> + valid_mask |=3D HCR_NV | HCR_AT; >>>> + if (!cpu_isar_feature(aa64_noe2h0_and_nv1_res0, cpu)) { >>>> + valid_mask |=3D HCR_NV1; >>>> + } >>>> } >>>> if (cpu_isar_feature(aa64_nv2, cpu)) { >>>> - valid_mask |=3D HCR_NV2; >>>> + valid_mask |=3D HCR_NV1 | HCR_NV2; >>>=20 >>> Why add NV1 here? >>=20 >> My reading was if you had FEAT_NV2 then HCR_NV1 was always valid >> whatever E2H0 might say. Unless we can validate we don't get >> contradictory ID values elsewhere? > KVM with nested virt enabled out of the box exposes a virtual machine with > VHE-only L1 and above, with no allowance for an nVHE nested guest past L1. > > In the Linux kernel in arch/arm64/kvm/nested.c: > > case SYS_ID_AA64MMFR4_EL1: > /* > * You get EITHER > * > * - FEAT_VHE without FEAT_E2H0 > * - FEAT_NV limited to FEAT_NV2 > * - HCR_EL2.NV1 being RES0 > * > * OR > * > * - FEAT_E2H0 without FEAT_VHE nor FEAT_NV > * > * Life is too short for anything else. > */ This is a choice a host can make to simplify things but we want to make sure we could represent hardware that makes a different choice. > > And after taking a further look at the machine readable spec*, 0b1110 is = valid together > with FEAT_NV2, as nothing there says otherwise. > > * > https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads Is this from the XML or the registers description? >>=20 >>=20 >> --=20 >> Alex Benn=C3=A9e >> Virtualisation Tech Lead @ Linaro --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro