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Mon, 2 Feb 2026 19:09:27 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id wTJTOWf2gGmSfAAAD6G6ig (envelope-from ); Mon, 02 Feb 2026 19:09:27 +0000 From: Fabiano Rosas To: Chao Liu , Alistair Francis , Daniel Henrique Barboza , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , Laurent Vivier , Paolo Bonzini , Tao Tang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, hust-os-kernel-patches@googlegroups.com, Chao Liu Subject: Re: [RFC PATCH v2 2/2] tests/qtest: Add RISC-V IOMMU bare-metal test In-Reply-To: <7cc1e085432336463dd19e11212cda516b97a33e.1769678103.git.chao.liu.zevorn@gmail.com> References: <7cc1e085432336463dd19e11212cda516b97a33e.1769678103.git.chao.liu.zevorn@gmail.com> Date: Mon, 02 Feb 2026 16:09:25 -0300 Message-ID: <87sebjq7x6.fsf@suse.de> MIME-Version: 1.0 Content-Type: text/plain X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[99.99%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_TLS_ALL(0.00)[]; ARC_NA(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; MISSING_XM_UA(0.00)[]; RCPT_COUNT_TWELVE(0.00)[13]; MIME_TRACE(0.00)[0:+]; TAGGED_RCPT(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; TO_DN_SOME(0.00)[]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[nongnu.org,googlegroups.com,gmail.com]; FREEMAIL_TO(0.00)[gmail.com,wdc.com,ventanamicro.com,dabbelt.com,linux.alibaba.com,redhat.com,phytium.com.cn]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:mid, suse.de:email, imap1.dmz-prg2.suse.org:helo] Received-SPF: pass client-ip=195.135.223.130; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Chao Liu writes: > Add a qtest suite for the RISC-V IOMMU PCI device on the virt machine. > The test exercises bare, S-stage, G-stage, and nested translation paths > using iommu-testdev and the qos-riscv-iommu helpers. > > The test validates: > - Device context (DC) configuration > - SV39 page table walks for S-stage translation > - SV39x4 page table walks for G-stage translation > - Nested translation combining both stages > - FCTL register constraints > > This provides regression coverage for the RISC-V IOMMU implementation > without requiring a full guest OS boot. > > Signed-off-by: Chao Liu ... > +static bool riscv_iommu_test_setup(RiscvIommuTestState *state) > +{ > + if (!qtest_has_machine("virt")) { > + g_test_skip("virt machine not available"); > + return false; > + } > + > + state->qts = qtest_init("-machine virt,acpi=off " > + "-cpu max -smp 1 -m 512 -net none " > + "-device riscv-iommu-pci " > + "-device iommu-testdev"); > + > + qpci_init_generic(&state->gbus, state->qts, NULL, false); > + riscv_config_qpci_bus(&state->gbus); > + > + state->iommu_dev = find_riscv_iommu_pci(&state->gbus, &state->iommu_base); > + g_assert(state->iommu_dev); > + > + state->testdev = find_iommu_testdev(&state->gbus, &state->testdev_bar); > + g_assert(state->testdev); > + These two will leak. Otherwise, looks good. Reviewed-by: Fabiano Rosas