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bh=NbAiRonudTxxn0Dt83kCP93jhH7iA1DD1uK9tgWHiiQ=; b=Dh6Tt8QA6S70Ghz0oNTxymUWY03z5vFwvRqdDkV12ToYE0rTRT08QfmezeuxMoIEqzcWl/ cEOByp9wkD/cwK1RWAGKqg/P3BdtUSIQFagOXeU7fr9kzHduCLwk0zrMbqdmYsThRS5iom vImynl8vkdYhu/jfi2lxvheeX46HtQ/5oKVKcLPZEC/iZbrlWi2YL1fKtcBBg2ryP1j/x8 05abcsmYL9k/3QBYaPhJ1Lsy+ZPq8aWpT7E1Oj0SPFKLP1B/DneTM8LkIniHVRlC3dNaB9 9JI4nf1d989RLkND0p9cHN/YkDpXNvu3lTyIEMxadnItlTGBThb01P+5SRg7Sg== From: Miquel Raynal To: Santhosh Kumar K Cc: , , , , , , , , , , , , Subject: Re: [RFC PATCH 01/10] spi: spi-mem: Introduce support for tuning controller In-Reply-To: <20250811193219.731851-2-s-k6@ti.com> (Santhosh Kumar K.'s message of "Tue, 12 Aug 2025 01:02:10 +0530") References: <20250811193219.731851-1-s-k6@ti.com> <20250811193219.731851-2-s-k6@ti.com> User-Agent: mu4e 1.12.7; emacs 30.1 Date: Wed, 10 Sep 2025 10:21:41 +0200 Message-ID: <87seguemzu.fsf@bootlin.com> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250910_012150_690752_CF44B5B7 X-CRM114-Status: GOOD ( 13.01 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; 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bh=NbAiRonudTxxn0Dt83kCP93jhH7iA1DD1uK9tgWHiiQ=; b=Dh6Tt8QA6S70Ghz0oNTxymUWY03z5vFwvRqdDkV12ToYE0rTRT08QfmezeuxMoIEqzcWl/ cEOByp9wkD/cwK1RWAGKqg/P3BdtUSIQFagOXeU7fr9kzHduCLwk0zrMbqdmYsThRS5iom vImynl8vkdYhu/jfi2lxvheeX46HtQ/5oKVKcLPZEC/iZbrlWi2YL1fKtcBBg2ryP1j/x8 05abcsmYL9k/3QBYaPhJ1Lsy+ZPq8aWpT7E1Oj0SPFKLP1B/DneTM8LkIniHVRlC3dNaB9 9JI4nf1d989RLkND0p9cHN/YkDpXNvu3lTyIEMxadnItlTGBThb01P+5SRg7Sg== From: Miquel Raynal To: Santhosh Kumar K Cc: , , , , , , , , , , , , Subject: Re: [RFC PATCH 01/10] spi: spi-mem: Introduce support for tuning controller In-Reply-To: <20250811193219.731851-2-s-k6@ti.com> (Santhosh Kumar K.'s message of "Tue, 12 Aug 2025 01:02:10 +0530") References: <20250811193219.731851-1-s-k6@ti.com> <20250811193219.731851-2-s-k6@ti.com> User-Agent: mu4e 1.12.7; emacs 30.1 Date: Wed, 10 Sep 2025 10:21:41 +0200 Message-ID: <87seguemzu.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 On 12/08/2025 at 01:02:10 +0530, Santhosh Kumar K wrote: > From: Pratyush Yadav > > Some controllers like the Cadence OSPI controller need to perform a > tuning sequence to operate at high data rates. Tuning is needs to happen > once the device is switched to appropriate mode (say 8S-8S-8S or > 8D-8D-8D). This is actually wrong. Tuning is way more generic than that :) If someone wants to use a chip at a high frequency (50MHz in your case, but whatever, there is a threshold above which additional care must be taken), it must go through the calibration step. It does not matter in which mode you are. Calibration would still be relevant in single SDR mode. This 50MHz bothered Mark because it is too Cadence specific. Maybe this should be a controller parameter? If the spi-mem core (or even the spi core, by extensino) sees that the design allows running at XMHz (due to the SPI peripheral properties or simply the absence of any limitation), and if the controller states that it requires an extra tuning step above YMHz (and X > Y), then it launches the calibration. >From a core perspective, I would like the calibration hook to be as simple as possible, because what "calibration" means is highly controller and chip specific. The Cadence SPI controller driver could request the pattern through the nvmem interface or maybe we can even include it in the kernel through some type of firmware interface (it could be stored anywhere) and if it gets it, it writes it to the device cache. Once done, it takes the fastest available read operation available for the chip and performs its calibration. The calibration hook no longer needs anything SPI driver specific. I don't know if still requires anything chip specific though (like the optimal read operation), but can you please try implementing that and then we'll discuss this further. Thanks, Miqu=C3=A8l