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Thu, 27 Feb 2025 02:10:20 -0800 (PST) Received: from draig.lan ([185.126.160.109]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b7a27abd6sm17209855e9.26.2025.02.27.02.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 02:10:19 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id E2ABD5F8AB; Thu, 27 Feb 2025 10:10:18 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: "Nicholas Piggin" Cc: "Richard Henderson" , , "Daniel Henrique Barboza" , "Igor Mammedov" , "Helge Deller" , "Paolo Bonzini" , , "Zhao Liu" Subject: Re: [PATCH 2/4] target/hppa: defer hppa_ptlbe until CPU starts running In-Reply-To: (Nicholas Piggin's message of "Thu, 27 Feb 2025 19:05:47 +1000") References: <20250225184628.3590671-1-alex.bennee@linaro.org> <20250225184628.3590671-3-alex.bennee@linaro.org> User-Agent: mu4e 1.12.9; emacs 29.4 Date: Thu, 27 Feb 2025 10:10:18 +0000 Message-ID: <87senzwved.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org "Nicholas Piggin" writes: > On Wed Feb 26, 2025 at 5:38 AM AEST, Richard Henderson wrote: >> On 2/25/25 11:33, Richard Henderson wrote: >>> On 2/25/25 10:46, Alex Benn=C3=A9e wrote: >>>> @@ -191,7 +199,7 @@ static void hppa_cpu_realizefn(DeviceState *dev, E= rror **errp) >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cpu->alarm_time= r =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 hppa_cpu_alarm_timer, cpu); >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 hppa_ptlbe(&cpu->env); >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 async_run_on_cpu(cs, hppa_= clear_ptlbe, RUN_ON_CPU_HOST_PTR(&cpu->env)); >>>=20 >>> Nack, this is emulation of hardware, not softmmu. >> >> Hmm. I see what you're thinking about though: this function, after rese= tting the data=20 >> structures associated with the hardware emulation, also calls the softmm= u flush. >> >> If we absolutely need to do so, I suppose delaying the hardware emulatio= n flush to the=20 >> work queue isn't the worst solution. This is where the hppa patch is mo= re correct than=20 >> the ppc patch which completely eliminated the hardware emulation flush. > > Could we expose a function that performs the hardware state reset, > and leave the TCG flushing to the TCG CPU reset? I did consider that - but the function is also called from helpers at which point you also do need to flush the softmmu TLB. However someone with better knowledge of the architecture might be able to do a slightly more refined flush (individual pages or mmuidxs) in those cases. > > Thanks, > Nick --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro