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Tue, 02 Apr 2024 08:01:22 +0200 From: Sven Schnelle To: Richard Henderson Cc: qemu-devel@nongnu.org, Helge Deller Subject: Re: [PATCH 2/3] target/hppa: mask offset bits in gva In-Reply-To: <87jzlm1334.fsf@t14.stackframe.org> (Sven Schnelle's message of "Thu, 28 Mar 2024 22:03:27 +0100") References: <20240324080945.991100-1-svens@stackframe.org> <20240324080945.991100-3-svens@stackframe.org> <87jzlm1334.fsf@t14.stackframe.org> Date: Tue, 02 Apr 2024 08:01:21 +0200 Message-ID: <87sf04xpzi.fsf@t14.stackframe.org> MIME-Version: 1.0 Content-Type: text/plain Received-SPF: pass client-ip=23.83.209.46; envelope-from=svens@stackframe.org; helo=cross.birch.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard, Sven Schnelle writes: > Richard Henderson writes: > >> On 3/23/24 22:09, Sven Schnelle wrote: >>> The CPU seems to mask a few bits in the offset when running >>> under HP-UX. ISR/IOR register contents for an address in >>> the processor HPA (0xfffffffffffa0000) on my C8000 and J6750: >>> running on Linux: 000000003fffffff c0000000fffa0500 >>> running on HP-UX: 00000000301fffff c0000000fffa0500 >>> I haven't found how this is switched (guess some diag in the >>> firmware), but linux + seabios seems to handle that as well, >>> so lets mask out the additional bits. >>> Signed-off-by: Sven Schnelle >>> [..] >> [..] >> Though my argument would suggest the mask should be 0xff for the >> 40-bit physical address, which is not what you see at all, so perhaps >> the thing is moot. I am at a loss to explain why or how HP-UX gets a >> 7-bit hole in the ISR result. >> >> On the other hand, there are some not-well-documented shenanigans (aka >> implementation defined behaviour) between Figure H-8 and Figure H-11, >> where the 62-bit absolute address is expanded to a 64-bit logical >> physical address and then compacted to a 40-bit implementation >> physical address. >> >> We've already got hacks in place for this in hppa_abs_to_phys_pa2_w1, >> which just truncates everything down to 40 bits. But that's probably >> not what the processor is really doing. > > I looked into this again, and it's caused by Space-ID hashing. HP-UX asks > PDC/Firmware how many bits are used for the hashing. seabios returns > zero, in which case HP-UX uses a default mask of 0xf01fffffffffffff. > By modifying seabios, i can make HP-UX use the appropriate mask, but > switching of SpaceID hashing entirely is impossible. The reason why > the CPU doesn't strip the bits when running linux is that Linux switches > of Space-ID hashing early in the startup code (before mm gets > initialized). > > My J6750 Firmware only returns two values: 0 when Space-ID hashing is > off, 0xfe0 when it is enabled. This is hardcoded in the firmware - the > only thing PDC checks is a bit in Debug Register 2, which enables > Space-ID hashing. 0xfe0 matches the 0xf01f... mask used by HP-UX > pretty well. > > So if qemu wants to run 64 Bit HP-UX the proper way, i guess it needs > to implement Space-ID hashing. I wonder wether it would be acceptable to implement this masking in a switchable way? This would mean: Implement dr2 and the mfdiag/mtdiag instructions. dr2 contains a bit which enables/disables space id hashing. Seabios would then set this bit when booting. Linux would disable it again during boot (this would be the same like on real hardware), while HP-UX would leave it enabled.