From: Thomas Gleixner <tglx@linutronix.de>
To: "James Tai [戴志峰]" <james.tai@realtek.com>,
"Marc Zyngier" <maz@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
kernel test robot <lkp@intel.com>,
Dan Carpenter <error27@gmail.com>
Subject: RE: [PATCH v3 2/6] irqchip: Add interrupt controller support for Realtek DHC SoCs
Date: Wed, 20 Dec 2023 16:30:48 +0100 [thread overview]
Message-ID: <87sf3wlwlz.ffs@tglx> (raw)
In-Reply-To: <d9556a14e8d64f83b89a2d1d231003f4@realtek.com>
On Tue, Dec 19 2023 at 03:15, James Tai [戴志峰] wrote:
>>On Wed, Nov 29 2023 at 13:43, James Tai wrote:
>>> +static inline void realtek_intc_clear_ints_bit(struct
>>> +realtek_intc_data *data, int bit) {
>>> + writel(BIT(bit) & ~1, data->base + data->info->isr_offset);
>>
>>That '& ~1' solves what aside of preventing bit 0 from being written?
>>
> The ISR register uses bit 0 to clear or set ISR status.
> Write 0 to clear bits and write 1 to set bits.
> Therefore, to clear the interrupt status, bit 0 should consistently be
> set to '0'.
And how does BIT(bit) with 1 <= bit <= 31 end up having bit 0 set?
Also a comment explaining the reasoning here would be helpful.
next prev parent reply other threads:[~2023-12-20 15:39 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-29 5:43 [PATCH v3 0/6] Initial support for the Realtek DHC SoCs James Tai
2023-11-29 5:43 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: Add support for " James Tai
2023-11-29 8:57 ` Krzysztof Kozlowski
2023-12-08 5:40 ` James Tai [戴志峰]
2023-11-29 5:43 ` [PATCH v3 2/6] irqchip: Add interrupt controller " James Tai
2023-11-29 8:21 ` Dan Carpenter
2023-11-29 13:21 ` Dan Carpenter
2023-12-08 8:21 ` James Tai [戴志峰]
2023-12-08 8:43 ` Dan Carpenter
2023-12-11 5:19 ` James Tai [戴志峰]
2023-11-29 15:41 ` Rob Herring
2023-12-11 5:19 ` James Tai [戴志峰]
2023-12-08 15:31 ` Thomas Gleixner
2023-12-19 3:15 ` James Tai [戴志峰]
2023-12-20 15:30 ` Thomas Gleixner [this message]
2023-12-22 6:20 ` James Tai [戴志峰]
2023-11-29 5:43 ` [PATCH v3 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver James Tai
2023-12-08 15:37 ` Thomas Gleixner
2023-12-19 5:51 ` James Tai [戴志峰]
2023-12-11 17:41 ` Rob Herring
2023-12-19 5:10 ` James Tai [戴志峰]
2023-11-29 5:43 ` [PATCH v3 4/6] irqchip: Introduce RTD1319D " James Tai
2023-11-29 5:43 ` [PATCH v3 5/6] irqchip: Introduce RTD1325 " James Tai
2023-11-29 5:43 ` [PATCH v3 6/6] irqchip: Introduce RTD1619B " James Tai
2023-12-08 15:41 ` Thomas Gleixner
2023-12-19 3:29 ` James Tai [戴志峰]
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