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Fri, 21 Jan 2022 09:07:10 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4D6FAB2072; Fri, 21 Jan 2022 09:07:10 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E6E85B213B; Fri, 21 Jan 2022 09:07:06 +0000 (GMT) Received: from skywalker.linux.ibm.com (unknown [9.43.32.214]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Fri, 21 Jan 2022 09:07:06 +0000 (GMT) X-Mailer: emacs 28.0.91 (via feedmail 11-beta-1 I) From: "Aneesh Kumar K.V" To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, linux-nvdimm@lists.01.org, dan.j.williams@intel.com Subject: Re: [PATCH v7 3/7] powerpc/pmem: Add flush routines using new pmem store and sync instruction In-Reply-To: <7eba6780-5ffd-54f4-feb0-b5e627ec6216@csgroup.eu> References: <20200701072235.223558-1-aneesh.kumar@linux.ibm.com> <20200701072235.223558-4-aneesh.kumar@linux.ibm.com> <7eba6780-5ffd-54f4-feb0-b5e627ec6216@csgroup.eu> Date: Fri, 21 Jan 2022 14:37:00 +0530 Message-ID: <87sftho3t7.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 2pSSl9DIMjjRUIg41UlrZBGrhwygNAWy X-Proofpoint-ORIG-GUID: MIGigJyuDxEsSAjusDTt-hF0xaYs0YNx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-21_06,2022-01-20_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 malwarescore=0 spamscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201210060 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: oohall@gmail.com, Jeff Moyer , msuchanek@suse.de, Jan Kara Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Christophe Leroy writes: > Le 01/07/2020 =C3=A0 09:22, Aneesh Kumar K.V a =C3=A9crit=C2=A0: >> Start using dcbstps; phwsync; sequence for flushing persistent memory ra= nge. >> The new instructions are implemented as a variant of dcbf and hwsync and= on >> P8 and P9 they will be executed as those instructions. We avoid using th= em on >> older hardware. This helps to avoid difficult to debug bugs. >>=20 > > Before this patch, the flush was done for all. > After this patch, IIUC the flush is done only on CPUs having feature=20 > CPU_FTR_ARCH_207S. > > What about other CPUs ? > > I don't know much about PMEM, my concern is about the UACCESS_FLUSHCACHE= =20 > API introduced by commit 6c44741d75a2 ("powerpc/lib: Implement=20 > UACCESS_FLUSHCACHE API") > > After your patch, __copy_from_user_flushcache() and memcpy_flushcache()=20 > are not doing cache flush anymore. > > Is that intended ? yes, with the understanding that these functions are used with persistent memory . We restrict the persistent memory usage to p8 and above via commit c83040192f3763b243ece26073d61a895b4a230f > > I'm trying to optimise some ALSA driver that does copy_from_user +=20 > cache_flush for DMA, and I was wondering if using=20 > __copy_from_user_flushcache() was an alternative. > > Or is it __copy_from_user_inatomic_nocache() which has to be done for tha= t ? > > Thanks > Christophe > > >> Signed-off-by: Aneesh Kumar K.V >> --- >> arch/powerpc/include/asm/cacheflush.h | 1 + >> arch/powerpc/lib/pmem.c | 50 ++++++++++++++++++++++++--- >> 2 files changed, 47 insertions(+), 4 deletions(-) >>=20 >> diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/includ= e/asm/cacheflush.h >> index de600b915a3c..54764c6e922d 100644 >> --- a/arch/powerpc/include/asm/cacheflush.h >> +++ b/arch/powerpc/include/asm/cacheflush.h >> @@ -6,6 +6,7 @@ >>=20=20=20 >> #include >> #include >> +#include >>=20=20=20 >> #ifdef CONFIG_PPC_BOOK3S_64 >> /* >> diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c >> index 0666a8d29596..5a61aaeb6930 100644 >> --- a/arch/powerpc/lib/pmem.c >> +++ b/arch/powerpc/lib/pmem.c >> @@ -9,20 +9,62 @@ >>=20=20=20 >> #include >>=20=20=20 >> +static inline void __clean_pmem_range(unsigned long start, unsigned lon= g stop) >> +{ >> + unsigned long shift =3D l1_dcache_shift(); >> + unsigned long bytes =3D l1_dcache_bytes(); >> + void *addr =3D (void *)(start & ~(bytes - 1)); >> + unsigned long size =3D stop - (unsigned long)addr + (bytes - 1); >> + unsigned long i; >> + >> + for (i =3D 0; i < size >> shift; i++, addr +=3D bytes) >> + asm volatile(PPC_DCBSTPS(%0, %1): :"i"(0), "r"(addr): "memory"); >> + >> + >> + asm volatile(PPC_PHWSYNC ::: "memory"); >> +} >> + >> +static inline void __flush_pmem_range(unsigned long start, unsigned lon= g stop) >> +{ >> + unsigned long shift =3D l1_dcache_shift(); >> + unsigned long bytes =3D l1_dcache_bytes(); >> + void *addr =3D (void *)(start & ~(bytes - 1)); >> + unsigned long size =3D stop - (unsigned long)addr + (bytes - 1); >> + unsigned long i; >> + >> + for (i =3D 0; i < size >> shift; i++, addr +=3D bytes) >> + asm volatile(PPC_DCBFPS(%0, %1): :"i"(0), "r"(addr): "memory"); >> + >> + >> + asm volatile(PPC_PHWSYNC ::: "memory"); >> +} >> + >> +static inline void clean_pmem_range(unsigned long start, unsigned long = stop) >> +{ >> + if (cpu_has_feature(CPU_FTR_ARCH_207S)) >> + return __clean_pmem_range(start, stop); >> +} >> + >> +static inline void flush_pmem_range(unsigned long start, unsigned long = stop) >> +{ >> + if (cpu_has_feature(CPU_FTR_ARCH_207S)) >> + return __flush_pmem_range(start, stop); >> +} >> + >> /* >> * CONFIG_ARCH_HAS_PMEM_API symbols >> */ >> void arch_wb_cache_pmem(void *addr, size_t size) >> { >> unsigned long start =3D (unsigned long) addr; >> - flush_dcache_range(start, start + size); >> + clean_pmem_range(start, start + size); >> } >> EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); >>=20=20=20 >> void arch_invalidate_pmem(void *addr, size_t size) >> { >> unsigned long start =3D (unsigned long) addr; >> - flush_dcache_range(start, start + size); >> + flush_pmem_range(start, start + size); >> } >> EXPORT_SYMBOL_GPL(arch_invalidate_pmem); >>=20=20=20 >> @@ -35,7 +77,7 @@ long __copy_from_user_flushcache(void *dest, const voi= d __user *src, >> unsigned long copied, start =3D (unsigned long) dest; >>=20=20=20 >> copied =3D __copy_from_user(dest, src, size); >> - flush_dcache_range(start, start + size); >> + clean_pmem_range(start, start + size); >>=20=20=20 >> return copied; >> } >> @@ -45,7 +87,7 @@ void *memcpy_flushcache(void *dest, const void *src, s= ize_t size) >> unsigned long start =3D (unsigned long) dest; >>=20=20=20 >> memcpy(dest, src, size); >> - flush_dcache_range(start, start + size); >> + clean_pmem_range(start, start + size); >>=20=20=20 >> return dest; >> }