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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
To: Idan Horowitz <idan.horowitz@gmail.com>
Cc: qemu-arm@nongnu.org
Subject: Re: DSB does not seem to wait for TLBI completion
Date: Wed, 01 Dec 2021 16:13:38 +0000
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Idan Horowitz <idan.horowitz@gmail.com> writes:

> Idan Horowitz <idan.horowitz@gmail.com> wrote:
>>
>> I am actually running in icount mode (-icount shift=3D10 specifically),
>> and adding the translation block exit or just using ISB directly does
>> not seem to affect it unfortunately.
>>
>> Idan Horowitz
>
> After a lot of testing I had the thought of trying this without
> icount, and it seems to work fine without it, so the issue is somehow
> related to icount being enabled.

That's is weird because icount basically ensures round robin scheduling
of each vCPU in turn. I wonder if there is a pending flush when the vCPU
switches?

We really need a reliable reproducer for this to investigate further.

>
> Idan Horowitz


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Alex Benn=C3=A9e