From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F1D6C433F5 for ; Thu, 28 Oct 2021 14:59:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F068E610F8 for ; Thu, 28 Oct 2021 14:59:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F068E610F8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gpgYfw6gthbjNpz0H66REIFk8aeTeZlVkkKG4+20A0Q=; b=JKsGRqJ5gAz/xK K8KoLkxBcwwLaKfn2rkVk8rV2e2EURKSBr9RgcvvVAZAe54N14K9qAdUSAFhFqipgjFdzOKKZ7c4U AF6HOtmulKFoiUH0vXtgyrUWiq3CY3NixSyR8ZhTPbr9kExnrwOah7+VFwcy/dyOi02luSplql5du BiiQg/LcmJBlx+XfHRw7sO1qO5R16AArbpkMw1JmJl11YGobSuO5D0jaoUFENkMVAc14x8m50eCqX KEE38tybC6kK7ddgf2sQRNfTSjyQDkQVcP6dbG+XwG6nQpoYC48VsviDQ5IYpBRRRFtGsidkIbjVC F2c/j8CQ3q7je+7UTtzw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mg6rq-008KIP-HF; Thu, 28 Oct 2021 14:58:58 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mg6rG-008Jwz-JC for linux-riscv@lists.infradead.org; Thu, 28 Oct 2021 14:58:24 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 55D9F6112F; Thu, 28 Oct 2021 14:58:22 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mg6rE-002ErX-DD; Thu, 28 Oct 2021 15:58:20 +0100 Date: Thu, 28 Oct 2021 15:58:19 +0100 Message-ID: <87sfwl9oxg.wl-maz@kernel.org> From: Marc Zyngier To: Nikita Shubin Cc: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT In-Reply-To: <20211028135523.5cf4b66b@redslave.neermore.group> References: <20211024013303.3499461-1-guoren@kernel.org> <20211024013303.3499461-4-guoren@kernel.org> <87a6ixbcse.wl-maz@kernel.org> <20211028135523.5cf4b66b@redslave.neermore.group> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: nikita.shubin@maquefel.me, guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211028_075822_713569_EDEDB278 X-CRM114-Status: GOOD ( 31.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, 28 Oct 2021 11:55:23 +0100, Nikita Shubin wrote: > > Hello Marc and Guo Ren! > > On Mon, 25 Oct 2021 11:48:33 +0100 > Marc Zyngier wrote: > > > On Sun, 24 Oct 2021 02:33:03 +0100, > > guoren@kernel.org wrote: > > > > > > From: Guo Ren > > > > > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the > > > driver, only the first interrupt could be handled, and continue irq > > > is blocked by hw. Because the thead,c900-plic couldn't complete > > > masked irq source which has been disabled in enable register. Add > > > thead_plic_chip which fix up c906-plic irq source completion > > > problem by unmask/mask wrapper. > > > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > > > The PLIC signals it has completed executing an interrupt handler by > > > writing the interrupt ID it received from the claim to the > > > claim/complete register. The PLIC does not check whether the > > > completion ID is the same as the last claim ID for that target. If > > > the completion ID does not match an interrupt source that is > > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ > > > completion is silently ignored. > > > > Given this bit of the spec... > > > > > +static void plic_thead_irq_eoi(struct irq_data *d) > > > +{ > > > + struct plic_handler *handler = > > > this_cpu_ptr(&plic_handlers); + > > > + if (irqd_irq_masked(d)) { > > > + plic_irq_unmask(d); > > > + writel(d->hwirq, handler->hart_base + > > > CONTEXT_CLAIM); > > > + plic_irq_mask(d); > > > + } else { > > > + writel(d->hwirq, handler->hart_base + > > > CONTEXT_CLAIM); > > > + } > > > +} > > > + > > > > ... it isn't obvious to me why this cannot happen on an SiFive PLIC. > > This indeed happens with SiFive PLIC. I am currently tinkering with > da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However > with changes proposed by Guo Ren in plic_thead_irq_eoi, everything > begins to work fine. > > May be these change should be propagated to plic_irq_eoi instead of > making a new function ? That's my impression too. I think the T-Head defect is pretty much immaterial when you consider how 'interesting' the PLIC architecture is. Conflating EOI and masking really is a misfeature... M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E56C9C433EF for ; Thu, 28 Oct 2021 14:58:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF4F261040 for ; Thu, 28 Oct 2021 14:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231380AbhJ1PAx (ORCPT ); Thu, 28 Oct 2021 11:00:53 -0400 Received: from mail.kernel.org ([198.145.29.99]:60552 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230451AbhJ1PAt (ORCPT ); Thu, 28 Oct 2021 11:00:49 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 55D9F6112F; Thu, 28 Oct 2021 14:58:22 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mg6rE-002ErX-DD; Thu, 28 Oct 2021 15:58:20 +0100 Date: Thu, 28 Oct 2021 15:58:19 +0100 Message-ID: <87sfwl9oxg.wl-maz@kernel.org> From: Marc Zyngier To: Nikita Shubin Cc: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT In-Reply-To: <20211028135523.5cf4b66b@redslave.neermore.group> References: <20211024013303.3499461-1-guoren@kernel.org> <20211024013303.3499461-4-guoren@kernel.org> <87a6ixbcse.wl-maz@kernel.org> <20211028135523.5cf4b66b@redslave.neermore.group> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: nikita.shubin@maquefel.me, guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 28 Oct 2021 11:55:23 +0100, Nikita Shubin wrote: > > Hello Marc and Guo Ren! > > On Mon, 25 Oct 2021 11:48:33 +0100 > Marc Zyngier wrote: > > > On Sun, 24 Oct 2021 02:33:03 +0100, > > guoren@kernel.org wrote: > > > > > > From: Guo Ren > > > > > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the > > > driver, only the first interrupt could be handled, and continue irq > > > is blocked by hw. Because the thead,c900-plic couldn't complete > > > masked irq source which has been disabled in enable register. Add > > > thead_plic_chip which fix up c906-plic irq source completion > > > problem by unmask/mask wrapper. > > > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > > > The PLIC signals it has completed executing an interrupt handler by > > > writing the interrupt ID it received from the claim to the > > > claim/complete register. The PLIC does not check whether the > > > completion ID is the same as the last claim ID for that target. If > > > the completion ID does not match an interrupt source that is > > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ > > > completion is silently ignored. > > > > Given this bit of the spec... > > > > > +static void plic_thead_irq_eoi(struct irq_data *d) > > > +{ > > > + struct plic_handler *handler = > > > this_cpu_ptr(&plic_handlers); + > > > + if (irqd_irq_masked(d)) { > > > + plic_irq_unmask(d); > > > + writel(d->hwirq, handler->hart_base + > > > CONTEXT_CLAIM); > > > + plic_irq_mask(d); > > > + } else { > > > + writel(d->hwirq, handler->hart_base + > > > CONTEXT_CLAIM); > > > + } > > > +} > > > + > > > > ... it isn't obvious to me why this cannot happen on an SiFive PLIC. > > This indeed happens with SiFive PLIC. I am currently tinkering with > da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However > with changes proposed by Guo Ren in plic_thead_irq_eoi, everything > begins to work fine. > > May be these change should be propagated to plic_irq_eoi instead of > making a new function ? That's my impression too. I think the T-Head defect is pretty much immaterial when you consider how 'interesting' the PLIC architecture is. Conflating EOI and masking really is a misfeature... M. -- Without deviation from the norm, progress is not possible.