From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0A8DC48BCF for ; Wed, 9 Jun 2021 14:36:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8C813613B1 for ; Wed, 9 Jun 2021 14:36:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8C813613B1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3630E6E420; Wed, 9 Jun 2021 14:36:19 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 18C8B6E420 for ; Wed, 9 Jun 2021 14:36:18 +0000 (UTC) IronPort-SDR: mbzXW0YM+GFq1rCZKzfS9/OV0MMCPVTd4aCayZosbezODnAzfXiu3BA3TxRUdIICMcKlHVKxbk qB+XvreXbtGQ== X-IronPort-AV: E=McAfee;i="6200,9189,10010"; a="204897489" X-IronPort-AV: E=Sophos;i="5.83,261,1616482800"; d="scan'208";a="204897489" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2021 07:36:17 -0700 IronPort-SDR: 8X6ytCusLKyv/NNia0KY/3CvXzDdBvVkwXVS7N/9FPDVY1ey/OJix7xw08MsoVcv0T14NmEaWv 9qqBysaPBNFg== X-IronPort-AV: E=Sophos;i="5.83,261,1616482800"; d="scan'208";a="482407261" Received: from ochaldek-mobl.ger.corp.intel.com (HELO localhost) ([10.252.34.111]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2021 07:36:15 -0700 From: Jani Nikula To: Stanislav Lisovskiy , intel-gfx@lists.freedesktop.org In-Reply-To: <20210603065038.7298-1-stanislav.lisovskiy@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20210603065038.7298-1-stanislav.lisovskiy@intel.com> Date: Wed, 09 Jun 2021 17:36:12 +0300 Message-ID: <87sg1ryujn.fsf@intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 03 Jun 2021, Stanislav Lisovskiy wrote: > CDCLK crawl feature allows to change CDCLK frequency > without disabling the actual PLL and doesn't require > a full modeset. I've pushed this to din because supposedly this is urgent. However, there are some issues, comments inline, please fix them afterwards. BR, Jani. > > v2: - Added has_cdclk_crawl as a feature flag to > intel_device_info(Matt Roper) > - s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/ > (Matt Roper) > > Cc: Mika Kahola > Signed-off-by: Stanislav Lisovskiy > Signed-off-by: Jani Nikula > Signed-off-by: Gwan-gyeong Mun > Cc: Stanislav Lisovskiy > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++--- > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 2 + > drivers/gpu/drm/i915/intel_device_info.h | 2 + > 4 files changed, 68 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 4656a6edc3be..f24bd9cf1318 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1547,6 +1547,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) > dev_priv->cdclk.hw.vco = vco; > } > > +static bool has_cdclk_crawl(struct drm_i915_private *i915) > +{ > + return INTEL_INFO(i915)->has_cdclk_crawl; > +} For everything else we use HAS_SOMETHING() in i915_drv.h, not local functions. [...] > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 1390fad5ec06..b326aff65cd6 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -185,6 +185,8 @@ struct intel_device_info { > > u8 abox_mask; > > + u8 has_cdclk_crawl; /* does support CDCLK crawling */ > + Flags are supposed to be added to DEV_INFO_FOR_EACH_FLAG() in intel_device_info.h. Or, actually, this one's about display, so DEV_INFO_DISPLAY_FOR_EACH_FLAG(). This makes them 1-bit bitfields instead of 8 bits, and automatically adds them to debug printouts. > #define DEFINE_FLAG(name) u8 name:1 > DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); > #undef DEFINE_FLAG -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx