From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC246C47254 for ; Tue, 5 May 2020 16:34:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9610020746 for ; Tue, 5 May 2020 16:34:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9610020746 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E0BE89F9F; Tue, 5 May 2020 16:34:44 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C42B89F9F for ; Tue, 5 May 2020 16:34:42 +0000 (UTC) IronPort-SDR: JL2mowHEV/iqzzPMsrCDoeajKuSKlk63ygpP+zFHSe0cDXGeiMj+D5Qut7mlkZhgBaDfai4HvG 9p1iXjYJaVPA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2020 09:34:40 -0700 IronPort-SDR: ECHYHir9U0ci3m5gkIGq2qSIwGUiJK9cv5X5MJv/koCxeLeIPef/Uriu76g5m8Elw+2306k3Dn 1S542+av3Vsg== X-IronPort-AV: E=Sophos;i="5.73,356,1583222400"; d="scan'208";a="259755733" Received: from dsp-dsk1.jf.intel.com (HELO localhost) ([10.54.70.63]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2020 09:34:40 -0700 From: D Scott Phillips To: Lionel Landwerlin , intel-gfx@lists.freedesktop.org In-Reply-To: References: <20200505000146.2295525-1-d.scott.phillips@intel.com> <874ksvtf86.fsf@intel.com> Date: Tue, 05 May 2020 09:32:07 -0700 Message-ID: <87sggecph4.fsf@intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Lionel Landwerlin writes: > On 05/05/2020 03:09, D Scott Phillips wrote: >> D Scott Phillips writes: >> >>> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 >>> pipe_control commands. HDC Pipeline flush actually resides in >>> dword 0, and the bit we were setting in dword 1 was Indirect State >>> Pointers Disable, which invalidates indirect state in the render >>> context. This causes failures for userspace, as things like push >>> constant state gets invalidated. >>> >>> Cc: Mika Kuoppala >>> Cc: Chris Wilson >>> Signed-off-by: D Scott Phillips >> also, >> >> Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush") >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > I think Mika sent the same patch in "drm/i915/gen12: Fix HDC pipeline > flush". > > -Lionel Ah, quite right, I missed it. Ignore this. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx