Re: [PATCH 1/2] drm/i915: Fix audio power up sequence for gen10/11

From: Jani Nikula <jani.nikula@intel.com>
To: Kai Vehmanen <kai.vehmanen@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: tiwai@suse.de
Subject: Re: [PATCH 1/2] drm/i915: Fix audio power up sequence for gen10/11
Date: Wed, 02 Oct 2019 17:33:30 +0300	[thread overview]
Message-ID: <87sgob9pz9.fsf@intel.com> (raw)
In-Reply-To: <20191001163555.24356-1-kai.vehmanen@linux.intel.com>

On Tue, 01 Oct 2019, Kai Vehmanen <kai.vehmanen@linux.intel.com> wrote:
> On gen10/11 platforms, driver must set the enable bit of AUD_PIN_BUF_CTL
> as part of audio power up sequence.
>
> Failing to do this resulted in errors during display audio codec probe,
> and failures during resume from suspend.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214
> Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 5 +++++
>  drivers/gpu/drm/i915/i915_reg.h            | 2 ++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 54638d99e021..a731af7ada08 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -862,6 +862,11 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
>  		/* Force CDCLK to 2*BCLK as long as we need audio powered. */
>  		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>  			glk_force_audio_cdclk(dev_priv, true);
> +
> +		if (INTEL_GEN(dev_priv) == 11 || INTEL_GEN(dev_priv) == 10)
> +			I915_WRITE(AUD_PIN_BUF_CTL,
> +				   (I915_READ(AUD_PIN_BUF_CTL) |
> +				    AUD_PIN_BUF_ENABLE));
>  	}
>  
>  	return ret;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 058aa5ca8b73..daff9058f0e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9133,6 +9133,8 @@ enum {
>  #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
>  
>  #define AUD_FREQ_CNTRL			_MMIO(0x65900)
> +#define AUD_PIN_BUF_CTL		_MMIO(0x48414)
> +#define   AUD_PIN_BUF_ENABLE		BIT(31)

Drive-by comment, please use REG_BIT() in i915_reg.h. BIT becomes UL
which in turn can cause trouble later on.

BR,
Jani.

>  
>  /*
>   * HSW - ICL power wells

-- 
Jani Nikula, Intel Open Source Graphics Center
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