diff for duplicates of <87shc3dqsj.fsf@free-electrons.com> diff --git a/a/1.txt b/N1/1.txt index 5a15a92..0bdc110 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,23 +1,23 @@ Hi Stephen, -=20 - On jeu., d=C3=A9c. 21 2017, Stephen Boyd <sboyd@codeaurora.org> wrote: + + On jeu., d?c. 21 2017, Stephen Boyd <sboyd@codeaurora.org> wrote: > On 11/30, Gregory CLEMENT wrote: >> Hi, ->>=20 +>> >> This small series is needed to use DVFS on Armada 37xx. When DVFS is >> enabled the CPU clock setting is done using an other set of registers >> from the North Bridge Power Management block. ->>=20 +>> >> The series adds the possibility to modify the CPU frequency using the >> associate load level matching the target frequency. However >> configuring the frequencies for each load is done by the cpufreq >> driver submitted in a separate series. ->>=20 +>> >> Obviously having both series (cpufreq and clk) is needed to support >> DVFS on Armada 37xx, but there is no dependencies between the series >> (for building or at runtime). ->>=20 +>> > > Are you relying on the clk API returning an error to detect if > DVFS is present or not? Just curious why that part of the code @@ -41,11 +41,11 @@ directly read the DVFS bit exposed through the syscon. Gregory > -> --=20 +> -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project ---=20 +-- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. diff --git a/a/content_digest b/N1/content_digest index ab08d58..6b4f98e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,47 +1,31 @@ "ref\020171130134029.20751-1-gregory.clement@free-electrons.com\0" "ref\020171221231341.GC7997@codeaurora.org\0" - "From\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0" - "Subject\0Re: [PATCH 0/3] Add DVFS support on CPU clock for Armada 37xx\0" + "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" + "Subject\0[PATCH 0/3] Add DVFS support on CPU clock for Armada 37xx\0" "Date\0Fri, 22 Dec 2017 11:02:04 +0100\0" - "To\0Stephen Boyd <sboyd@codeaurora.org>\0" - "Cc\0Mike Turquette <mturquette@baylibre.com>" - linux-clk@vger.kernel.org - linux-kernel@vger.kernel.org - Jason Cooper <jason@lakedaemon.net> - Andrew Lunn <andrew@lunn.ch> - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - linux-arm-kernel@lists.infradead.org - Antoine Tenart <antoine.tenart@free-electrons.com> - " Miqu\303\250l Raynal <miquel.raynal@free-electrons.com>" - Nadav Haklai <nadavh@marvell.com> - Victor Gu <xigu@marvell.com> - Marcin Wojtas <mw@semihalf.com> - Wilson Ding <dingwei@marvell.com> - Hua Jing <jinghua@marvell.com> - " Neta Zur Hershkovits <neta@marvell.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Stephen,\n" - "=20\n" - " On jeu., d=C3=A9c. 21 2017, Stephen Boyd <sboyd@codeaurora.org> wrote:\n" + " \n" + " On jeu., d?c. 21 2017, Stephen Boyd <sboyd@codeaurora.org> wrote:\n" "\n" "> On 11/30, Gregory CLEMENT wrote:\n" ">> Hi,\n" - ">>=20\n" + ">> \n" ">> This small series is needed to use DVFS on Armada 37xx. When DVFS is\n" ">> enabled the CPU clock setting is done using an other set of registers\n" ">> from the North Bridge Power Management block.\n" - ">>=20\n" + ">> \n" ">> The series adds the possibility to modify the CPU frequency using the\n" ">> associate load level matching the target frequency. However\n" ">> configuring the frequencies for each load is done by the cpufreq\n" ">> driver submitted in a separate series.\n" - ">>=20\n" + ">> \n" ">> Obviously having both series (cpufreq and clk) is needed to support\n" ">> DVFS on Armada 37xx, but there is no dependencies between the series\n" ">> (for building or at runtime).\n" - ">>=20\n" + ">> \n" ">\n" "> Are you relying on the clk API returning an error to detect if\n" "> DVFS is present or not? Just curious why that part of the code\n" @@ -65,14 +49,14 @@ "Gregory\n" "\n" ">\n" - "> --=20\n" + "> -- \n" "> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" "> a Linux Foundation Collaborative Project\n" "\n" - "--=20\n" + "-- \n" "Gregory Clement, Free Electrons\n" "Kernel, drivers, real-time and embedded Linux\n" "development, consulting, training and support.\n" http://free-electrons.com -ded2f431f36235175c6ec97b8aface5521b6d7fdbd855ae6ab1df004c7221d37 +f41040868f1d4c9e2bd40f65f49afa89b3954512cacbcdd4190fbb0fd928ac61
diff --git a/a/1.txt b/N2/1.txt index 5a15a92..8e7e4c4 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,23 +1,23 @@ Hi Stephen, -=20 - On jeu., d=C3=A9c. 21 2017, Stephen Boyd <sboyd@codeaurora.org> wrote: + + On jeu., déc. 21 2017, Stephen Boyd <sboyd@codeaurora.org> wrote: > On 11/30, Gregory CLEMENT wrote: >> Hi, ->>=20 +>> >> This small series is needed to use DVFS on Armada 37xx. When DVFS is >> enabled the CPU clock setting is done using an other set of registers >> from the North Bridge Power Management block. ->>=20 +>> >> The series adds the possibility to modify the CPU frequency using the >> associate load level matching the target frequency. However >> configuring the frequencies for each load is done by the cpufreq >> driver submitted in a separate series. ->>=20 +>> >> Obviously having both series (cpufreq and clk) is needed to support >> DVFS on Armada 37xx, but there is no dependencies between the series >> (for building or at runtime). ->>=20 +>> > > Are you relying on the clk API returning an error to detect if > DVFS is present or not? Just curious why that part of the code @@ -41,11 +41,11 @@ directly read the DVFS bit exposed through the syscon. Gregory > -> --=20 +> -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project ---=20 +-- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. diff --git a/a/content_digest b/N2/content_digest index ab08d58..a882a40 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -23,25 +23,25 @@ "\00:1\0" "b\0" "Hi Stephen,\n" - "=20\n" - " On jeu., d=C3=A9c. 21 2017, Stephen Boyd <sboyd@codeaurora.org> wrote:\n" + " \n" + " On jeu., d\303\251c. 21 2017, Stephen Boyd <sboyd@codeaurora.org> wrote:\n" "\n" "> On 11/30, Gregory CLEMENT wrote:\n" ">> Hi,\n" - ">>=20\n" + ">> \n" ">> This small series is needed to use DVFS on Armada 37xx. When DVFS is\n" ">> enabled the CPU clock setting is done using an other set of registers\n" ">> from the North Bridge Power Management block.\n" - ">>=20\n" + ">> \n" ">> The series adds the possibility to modify the CPU frequency using the\n" ">> associate load level matching the target frequency. However\n" ">> configuring the frequencies for each load is done by the cpufreq\n" ">> driver submitted in a separate series.\n" - ">>=20\n" + ">> \n" ">> Obviously having both series (cpufreq and clk) is needed to support\n" ">> DVFS on Armada 37xx, but there is no dependencies between the series\n" ">> (for building or at runtime).\n" - ">>=20\n" + ">> \n" ">\n" "> Are you relying on the clk API returning an error to detect if\n" "> DVFS is present or not? Just curious why that part of the code\n" @@ -65,14 +65,14 @@ "Gregory\n" "\n" ">\n" - "> --=20\n" + "> -- \n" "> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" "> a Linux Foundation Collaborative Project\n" "\n" - "--=20\n" + "-- \n" "Gregory Clement, Free Electrons\n" "Kernel, drivers, real-time and embedded Linux\n" "development, consulting, training and support.\n" http://free-electrons.com -ded2f431f36235175c6ec97b8aface5521b6d7fdbd855ae6ab1df004c7221d37 +bfe04eec34ce5dc77c7ee0a194c673875188fc338d73b28f58ecf6ea5ce8316a
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