From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1RV3-0007FC-Lq for qemu-devel@nongnu.org; Tue, 01 Nov 2016 01:20:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c1RUy-0006c6-Ol for qemu-devel@nongnu.org; Tue, 01 Nov 2016 01:20:41 -0400 Received: from mail-yw0-x243.google.com ([2607:f8b0:4002:c05::243]:35300) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c1RUy-0006bY-I0 for qemu-devel@nongnu.org; Tue, 01 Nov 2016 01:20:36 -0400 Received: by mail-yw0-x243.google.com with SMTP id h14so5117083ywa.2 for ; Mon, 31 Oct 2016 22:20:35 -0700 (PDT) References: <20161027151030.20863-1-alex.bennee@linaro.org> <20161027151030.20863-29-alex.bennee@linaro.org> From: Pranith Kumar In-reply-to: <20161027151030.20863-29-alex.bennee@linaro.org> Date: Tue, 01 Nov 2016 01:20:32 -0400 Message-ID: <87shrbzsgv.fsf@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v5 28/33] cputlb: make tlb_flush_by_mmuidx safe for MTTCG List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?utf-8?Q?Benn=C3=A9e?= Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, mttcg@listserver.greensocs.com, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, nikunj@linux.vnet.ibm.com, mark.burton@greensocs.com, jan.kiszka@siemens.com, serge.fdrv@gmail.com, rth@twiddle.net, peter.maydell@linaro.org, claudio.fontana@huawei.com, Peter Crosthwaite Hi Alex, Alex Bennée writes: > These flushes allow a per-mmuidx granularity to the TLB flushing and are > currently only used by the ARM model. As it is possible to hammer the > other vCPU threads with flushes (and build up long queues of identical > flushes) we extend mechanism used for the global tlb_flush and set a > bitmap describing all the pending flushes. The updates are done > atomically to avoid corruption of the bitmap but repeating a flush is > certainly not a problem. > > Signed-off-by: Alex Bennée > > static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) > @@ -233,16 +288,50 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) > } > } > > -void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) > +/* As we are going to hijack the bottom bits of the page address for a > + * mmuidx bit mask we need to fail to build if we can't do that > + */ > +QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS); > + FYI, this is causing a build error on my system with gcc 6.2. CC aarch64-softmmu/cputlb.o In file included from /home/pranith/devops/code/qemu/include/qemu/osdep.h:36:0, from /home/pranith/devops/code/qemu/cputlb.c:20: /home/pranith/devops/code/qemu/include/exec/cpu-all.h:196:26: error: braced-group within expression allowed only inside a function #define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \ ^ /home/pranith/devops/code/qemu/include/qemu/compiler.h:89:54: note: in definition of macro ‘QEMU_BUILD_BUG_ON’ typedef char glue(qemu_build_bug_on__,__LINE__)[(x)?-1:1] __attribute__((unused)); ^ /home/pranith/devops/code/qemu/cputlb.c:293:34: note: in expansion of macro ‘TARGET_PAGE_BITS’ QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS); ^~~~~~~~~~~~~~~~ /home/pranith/devops/code/qemu/rules.mak:60: recipe for target 'cputlb.o' failed make[1]: *** [cputlb.o] Error 1 Makefile:202: recipe for target 'subdir-aarch64-softmmu' failed make: *** [subdir-aarch64-softmmu] Error 2 Thanks, -- Pranith