Re: [PATCH V2 2/5] powerpc/mm: Add radix flush all with IS=3

["Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>]

Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:

> On Fri, 2016-08-19 at 14:22 +0530, Aneesh Kumar K.V wrote:
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> =C2=A0arch/powerpc/include/asm/book3s/64/tlbflush-radix.h |=C2=A0=C2=A01=
 +
>> =C2=A0arch/powerpc/mm/tlb-radix.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0| 15
>> +++++++++++++++
>> =C2=A02 files changed, 16 insertions(+)
>
> Don't we need two ? One for partition scoped and one for process scoped
> ?


With invalid selector value 3 (IS =3D 3), we will invalidate all entries
when executed with MSR[HV] =3D 1. I guess that should take out all the
translation cache, including implementation dependent one ?

Also note thar PRS =3D 0. ie, we are partition scoped. ie, we are doing
invalidate with

PRS =3D0, IS =3D 3 HV =3D 1 RIC =3D 2

>
>> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>> b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>> index 65037762b120..a9e19cb2f7c5 100644
>> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>> @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct
>> mm_struct *mm, unsigned long vmad
>> =C2=A0extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned
>> long gpa,
>> =C2=A0				=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0unsigned long page_size);
>> =C2=A0extern void radix__flush_tlb_lpid(unsigned long lpid);
>> +extern void radix__flush_tlb_all(void);
>> =C2=A0#endif
>> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-
>> radix.c
>> index 48df05ef5231..517feb47ebe4 100644
>> --- a/arch/powerpc/mm/tlb-radix.c
>> +++ b/arch/powerpc/mm/tlb-radix.c
>> @@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct
>> vm_area_struct *vma,
>> =C2=A0	radix__flush_tlb_range_psize(vma->vm_mm, start, end,
>> MMU_PAGE_2M);
>> =C2=A0}
>> =C2=A0EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
>> +
>> +void radix__flush_tlb_all(void)
>> +{
>> +	unsigned long rb,prs,r;
>> +	unsigned long ric =3D RIC_FLUSH_ALL;
>> +
>> +	rb =3D 0x3 << PPC_BITLSHIFT(53); /* IS =3D 3 */
>> +	prs =3D 0; /* partition scoped */
>> +	r =3D 1;=C2=A0=C2=A0=C2=A0/* raidx format */
>> +
>> +	asm volatile("ptesync": : :"memory");
>> +	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
>> +		=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0: : "r"(rb), "i"(r), "i"(prs), "i"(ric)=
, "r"(0)
>> : "memory");
>> +	asm volatile("eieio; tlbsync; ptesync": : :"memory");
>> +}