From: "Alex Bennée" <alex.bennee@linaro.org>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v1 3/4] target-arm: A64: Fix a typo whendeclaring TLBI opss
Date: Thu, 01 May 2014 09:59:08 +0100 [thread overview]
Message-ID: <87siotri1v.fsf@linaro.org> (raw)
In-Reply-To: <1398926097-28097-4-git-send-email-edgar.iglesias@gmail.com>
Edgar E. Iglesias <edgar.iglesias@gmail.com> writes:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Harmless typo as opc1 defaults to zero and opc2 gets
> re-declared to its correct value.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target-arm/helper.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 330bfc7..0b8e8aa 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1893,51 +1893,51 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .access = PL1_W, .type = ARM_CP_NOP },
> /* TLBI operations */
> { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbiall_write },
> { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_va_write },
> { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_asid_write },
> { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_vaa_write },
> { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_va_write },
> { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_vaa_write },
> { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbiall_write },
> { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_va_write },
> { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_asid_write },
> { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_vaa_write },
> { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_va_write },
> { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_vaa_write },
> #ifndef CONFIG_USER_ONLY
--
Alex Bennée
next prev parent reply other threads:[~2014-05-01 8:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-01 6:34 [Qemu-devel] [PATCH v1 0/4] Mixed ARM A64 fixes Edgar E. Iglesias
2014-05-01 6:34 ` [Qemu-devel] [PATCH v1 1/4] target-arm: Make vbar_write 64bit friendly on 32bit hosts Edgar E. Iglesias
2014-05-01 9:04 ` [Qemu-devel] [PATCH v1 1/4] target-arm: Make vbar_write 64bitfriendly on 32bit hostss Alex Bennée
2014-05-01 12:55 ` [Qemu-devel] [PATCH v1 1/4] target-arm: Make vbar_write 64bit friendly on 32bit hosts Peter Crosthwaite
2014-05-01 6:34 ` [Qemu-devel] [PATCH v1 2/4] target-arm: A64: Handle blr lr Edgar E. Iglesias
2014-05-01 9:02 ` Alex Bennée
2014-05-01 9:31 ` Peter Maydell
2014-05-01 11:43 ` Edgar E. Iglesias
2014-05-01 13:55 ` Alex Bennée
2014-05-01 6:34 ` [Qemu-devel] [PATCH v1 3/4] target-arm: A64: Fix a typo when declaring TLBI ops Edgar E. Iglesias
2014-05-01 8:59 ` Alex Bennée [this message]
2014-05-01 6:34 ` [Qemu-devel] [PATCH v1 4/4] target-arm: Correct a comment refering to EL0 Edgar E. Iglesias
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