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Korinsky To: Chinmay Rath Cc: shivangu@linux.ibm.com, adityag@linux.ibm.com, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, milesg@linux.ibm.com, brad@comstyle.com Subject: Re: [PATCH v4] powernv: boot OpenBSD on POWER9 In-Reply-To: References: <20260719145559.94342-1-kirill@korins.ky> User-Agent: Wanderlust Mail-Followup-To: rathc@linux.ibm.com, shivangu@linux.ibm.com, adityag@linux.ibm.com, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, milesg@linux.ibm.com, brad@comstyle.com, Kirill A. Korinsky MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Received-SPF: pass client-ip=162.55.82.72; envelope-from=kirill@korins.ky; helo=mx1.catap.net X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 20 Aug 2026 12:49:36 +0200, Chinmay Rath wrote: > > > On 7/19/26 20:25, Kirill A. Korinsky wrote: > > The POWER9 Processor User's Manual, section 4.9.4, specifies that POWER9 > > ignores PTCR[PATS] and only supports a 64 KiB partition table. Use an > > effective PATS value of 4 on POWER9; other processors keep the existing > > ISA v3.0 interpretation. > > > > The PSI model now exposes POWER9 IRQ level and pending status registers, > > and keeps both updated while delivering through the existing XIVE LSI > > source. This lets guests that select the POWER9 PSI LSI IRQ method > > continue to receive LPC interrupts. > > > > The blast radius is probably minimal: the PTCR change is limited to > > POWER9, while the PSI change only touches POWER9 PSI state and reuses > > the existing delivery path. > is missing :) Oops, shall I send a v5 version with: Signed-off-by: Kirill A. Korinsky or it's ok? > > --- > > hw/ppc/pnv_psi.c | 11 ++++-- > > target/ppc/mmu-book3s-v3.c | 21 +++++++++-- > > tests/functional/ppc64/meson.build | 2 + > > tests/functional/ppc64/test_openbsd.py | 52 ++++++++++++++++++++++++++ > > 4 files changed, 79 insertions(+), 7 deletions(-) > > create mode 100755 tests/functional/ppc64/test_openbsd.py > > > > diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c > > index e8701c6100..39ec448f3c 100644 > > --- a/hw/ppc/pnv_psi.c > > +++ b/hw/ppc/pnv_psi.c > > @@ -688,6 +688,8 @@ static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size) > > case PSIHB9_ESB_CI_BASE: > > case PSIHB9_ESB_NOTIF_ADDR: > > case PSIHB9_IVT_OFFSET: > > + case PSIHB9_IRQ_LEVEL: > > + case PSIHB9_IRQ_STAT: > > val = psi->regs[reg]; > > break; > > default: > > @@ -818,17 +820,20 @@ static void pnv_psi_power9_set_irq(void *opaque, int irq, int state) > > { > > PnvPsi *psi = opaque; > > uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; > > + uint64_t irq_bit = PPC_BIT(irq); > > if (irq_method & PSIHB9_IRQ_METHOD) { > > qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); > > return; > > } > > - /* Update LSI levels */ > > + /* Update LSI levels and pending status */ > > if (state) { > > - psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); > > + psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= irq_bit; > > + psi->regs[PSIHB_REG(PSIHB9_IRQ_STAT)] |= irq_bit; > > } else { > > - psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); > > + psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~irq_bit; > > + psi->regs[PSIHB_REG(PSIHB9_IRQ_STAT)] &= ~irq_bit; > > } > > qemu_set_irq(psi->qirqs[irq], state); > > diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c > > index 3865556310..f329a7a0f2 100644 > > --- a/target/ppc/mmu-book3s-v3.c > > +++ b/target/ppc/mmu-book3s-v3.c > > @@ -23,24 +23,37 @@ > > #include "mmu-hash64.h" > > #include "mmu-book3s-v3.h" > > +#define PPC64_V3_PATE_SIZE 16 /* two 64-bit words */ > > + > > bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) > > { > > uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB; > > uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS; > > + uint64_t table_size; > > + uint64_t entries; > > + > > + /* > > + * The POWER9 Processor User's Manual, section 4.9.4, specifies that > > + * POWER9 ignores PTCR[PATS] and only supports a 64 KiB partition table. > > + */ > > + if (cpu->env.excp_model == POWERPC_EXCP_POWER9) { > > + pats = 4; > > + } > > + table_size = 1ULL << (pats + 12); > > /* Check if partition table is properly aligned */ > > - if (patb & MAKE_64BIT_MASK(0, pats + 12)) { > > + if (patb & (table_size - 1)) { > > return false; > > } > > /* Calculate number of entries */ > > - pats = 1ull << (pats + 12 - 4); > > - if (pats <= lpid) { > > + entries = table_size / PPC64_V3_PATE_SIZE; > > + if (entries <= lpid) { > > return false; > > } > > /* Grab entry */ > > - patb += 16 * lpid; > > + patb += PPC64_V3_PATE_SIZE * lpid; > > entry->dw0 = ldq_phys(CPU(cpu)->as, patb); > > entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); > > return true; > > diff --git a/tests/functional/ppc64/meson.build b/tests/functional/ppc64/meson.build > > index f0f8ab8f61..cb3c745624 100644 > > --- a/tests/functional/ppc64/meson.build > > +++ b/tests/functional/ppc64/meson.build > > @@ -4,6 +4,7 @@ test_ppc64_timeouts = { > > 'fadump' : 480, > > 'hv' : 1000, > > 'mac99' : 120, > > + 'openbsd' : 240, > > 'powernv' : 480, > > 'pseries' : 480, > > 'replay' : 210, > > @@ -20,6 +21,7 @@ tests_ppc64_system_thorough = [ > > 'fadump', > > 'hv', > > 'mac99', > > + 'openbsd', > > 'powernv', > > 'pseries', > > 'replay', > > diff --git a/tests/functional/ppc64/test_openbsd.py b/tests/functional/ppc64/test_openbsd.py > > new file mode 100755 > > index 0000000000..bdbef6bf82 > > --- /dev/null > > +++ b/tests/functional/ppc64/test_openbsd.py > > @@ -0,0 +1,52 @@ > > +#!/usr/bin/env python3 > > +# > > +# Test that OpenBSD boots on a ppc powernv machine and reaches the installer. > > +# > > +# SPDX-License-Identifier: GPL-2.0-or-later > > + > > +from qemu_test import QemuSystemTest, Asset > > +from qemu_test import wait_for_console_pattern > > + > > + > > +class OpenBSDPowerNV(QemuSystemTest): > > + > > + ASSET_MINIROOT = Asset( > > + 'https://kirill.korins.ky/pub/qemu-powerpc64-openbsd/miniroot79.img', > > + '7829e42b75d81cafd732038b9d63228b79c1f5828d8375872a4bb655e1d6b13c') > > + > > + ASSET_BOOTKERNEL = Asset( > > + 'https://kirill.korins.ky/pub/qemu-powerpc64-openbsd/pnor.BOOTKERNEL', > > + '397ce43ce61910e1a2c4f13d301f957e61513a9ec5371bc3e87d3095411fae7b') > > + > > + def test_powernv9_openbsd_installer(self): > > + self.set_machine('powernv9') > > + self.require_accelerator('tcg') > > + > > + miniroot_path = self.ASSET_MINIROOT.fetch() > > + bootkernel_path = self.ASSET_BOOTKERNEL.fetch() > > + > > + self.vm.set_console() > > + self.vm.add_args('-cpu', 'power9', > > + '-accel', 'tcg,thread=single', > > + '-smp', '1,cores=1,threads=1', > > + '-m', '2g', > > + '-kernel', bootkernel_path, > > + '-device', > > + 'ich9-ahci,id=sata0,bus=pcie.0,addr=0x0', > > + '-drive', > > + f'file={miniroot_path},format=raw,if=none,' > > + 'id=bootdisk,snapshot=on', > > + '-device', > > + 'ide-hd,bus=sata0.0,unit=0,drive=bootdisk,' > > + 'bootindex=1') > > + self.vm.launch() > > + > > + wait_for_console_pattern(self, 'OpenBSD 7.9 (RAMDISK)', 'panic:') > > + wait_for_console_pattern( > > + self, > > + '(I)nstall, (U)pgrade, (A)utoinstall or (S)hell?', > > + 'panic:') > > + > > + > > +if __name__ == '__main__': > > + QemuSystemTest.main() -- wbr, Kirill