From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 1/7] tcg: Add integer min/max opcodes
Date: Wed, 12 Aug 2026 09:42:44 +0100 [thread overview]
Message-ID: <87tsoz20hn.fsf@draig.linaro.org> (raw)
In-Reply-To: <20260812003143.225228-2-richard.henderson@linaro.org> (Richard Henderson's message of "Tue, 11 Aug 2026 17:31:37 -0700")
Richard Henderson <richard.henderson@linaro.org> writes:
> We already have these for vectors; replicate for integers.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-opc.h | 4 +++
> tcg/tcg-op.c | 48 ++++++++++++++++++++++++++------
> tcg/tcg.c | 4 +++
> docs/devel/tcg-ops.rst | 14 +++++++++-
> tcg/aarch64/tcg-target.c.inc | 16 +++++++++++
> tcg/loongarch64/tcg-target.c.inc | 16 +++++++++++
> tcg/ppc64/tcg-target.c.inc | 16 +++++++++++
> tcg/riscv64/tcg-target.c.inc | 16 +++++++++++
> tcg/s390x/tcg-target.c.inc | 16 +++++++++++
> tcg/sparc64/tcg-target.c.inc | 16 +++++++++++
> tcg/tci/tcg-target.c.inc | 16 +++++++++++
> tcg/x86_64/tcg-target.c.inc | 16 +++++++++++
> 12 files changed, 189 insertions(+), 9 deletions(-)
>
> diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
> index 13c7f17f76..f3a81d5d7f 100644
> --- a/include/tcg/tcg-opc.h
> +++ b/include/tcg/tcg-opc.h
> @@ -89,11 +89,15 @@ DEF(setcond, 1, 2, 1, TCG_OPF_INT)
> DEF(sextract, 1, 1, 2, TCG_OPF_INT)
> DEF(shl, 1, 2, 0, TCG_OPF_INT)
> DEF(shr, 1, 2, 0, TCG_OPF_INT)
> +DEF(smax, 1, 2, 0, TCG_OPF_INT)
> +DEF(smin, 1, 2, 0, TCG_OPF_INT)
> DEF(st8, 0, 2, 1, TCG_OPF_INT)
> DEF(st16, 0, 2, 1, TCG_OPF_INT)
> DEF(st32, 0, 2, 1, TCG_OPF_INT)
> DEF(st, 0, 2, 1, TCG_OPF_INT)
> DEF(sub, 1, 2, 0, TCG_OPF_INT)
> +DEF(umax, 1, 2, 0, TCG_OPF_INT)
> +DEF(umin, 1, 2, 0, TCG_OPF_INT)
> DEF(xor, 1, 2, 0, TCG_OPF_INT)
>
> DEF(addco, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT)
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index c302a484cd..e28944cf72 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -1294,22 +1294,38 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg)
>
> void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
> {
> - tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b);
> + if (tcg_op_supported(INDEX_op_smin, TCG_TYPE_I32, 0)) {
> + tcg_gen_op3_i32(INDEX_op_smin, ret, a, b);
> + } else {
> + tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b);
> + }
> }
>
> void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
> {
> - tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b);
> + if (tcg_op_supported(INDEX_op_umin, TCG_TYPE_I32, 0)) {
> + tcg_gen_op3_i32(INDEX_op_umin, ret, a, b);
> + } else {
> + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b);
> + }
> }
>
> void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
> {
> - tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a);
> + if (tcg_op_supported(INDEX_op_smax, TCG_TYPE_I32, 0)) {
> + tcg_gen_op3_i32(INDEX_op_smax, ret, a, b);
> + } else {
> + tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a);
> + }
> }
>
> void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
> {
> - tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a);
> + if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I32, 0)) {
> + tcg_gen_op3_i32(INDEX_op_umax, ret, a, b);
> + } else {
> + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a);
> + }
> }
>
> void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a)
> @@ -2473,22 +2489,38 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
>
> void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
> {
> - tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b);
> + if (tcg_op_supported(INDEX_op_smin, TCG_TYPE_I64, 0)) {
> + tcg_gen_op3_i64(INDEX_op_smin, ret, a, b);
> + } else {
> + tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b);
> + }
> }
>
> void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
> {
> - tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b);
> + if (tcg_op_supported(INDEX_op_umin, TCG_TYPE_I64, 0)) {
> + tcg_gen_op3_i64(INDEX_op_umin, ret, a, b);
> + } else {
> + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b);
> + }
> }
>
> void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
> {
> - tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a);
> + if (tcg_op_supported(INDEX_op_smax, TCG_TYPE_I64, 0)) {
> + tcg_gen_op3_i64(INDEX_op_smax, ret, a, b);
> + } else {
> + tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a);
> + }
> }
>
> void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
> {
> - tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a);
> + if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I64, 0)) {
> + tcg_gen_op3_i64(INDEX_op_umax, ret, a, b);
> + } else {
> + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a);
> + }
> }
>
> void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a)
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 4c2207c6af..54f7906cb7 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -5512,6 +5512,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> case INDEX_op_sar:
> case INDEX_op_shl:
> case INDEX_op_shr:
> + case INDEX_op_smax:
> + case INDEX_op_smin:
> + case INDEX_op_umax:
> + case INDEX_op_umin:
> case INDEX_op_xor:
> {
> const TCGOutOpBinary *out =
> diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
> index f2e9255dd9..d30db9ea65 100644
> --- a/docs/devel/tcg-ops.rst
> +++ b/docs/devel/tcg-ops.rst
> @@ -317,6 +317,18 @@ Arithmetic
> pass 0 to *nh* to make a simple zero-extension of *nl*,
> so overflow should never occur.
>
> + * - smax *t0*, *t1*, *t2*
> +
> + umax *t0*, *t1*, *t2*
> +
> + - | *t0* = MAX(*t1*, *t2*), for signed and unsigned integers.
> +
> + * - smin *t0*, *t1*, *t2*
> +
> + umin *t0*, *t1*, *t2*
> +
> + - | *t0* = MIN(*t1*, *t2*), for signed and unsigned integers.
> +
> Logical
> -------
>
> @@ -512,7 +524,7 @@ Misc
>
> - | Reverse the 64 bits of input *t1* with output in *dest*.
>
> -Conditional moves
> +Conditional motes
> -----------------
A typo snuck in....
Otherwise:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
next prev parent reply other threads:[~2026-08-12 8:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-12 0:31 [PATCH 0/7] tcg: Add min/max opcodes Richard Henderson
2026-08-12 0:31 ` [PATCH 1/7] tcg: Add integer " Richard Henderson
2026-08-12 8:42 ` Alex Bennée [this message]
2026-08-12 0:31 ` [PATCH 2/7] tcg/optimize: Handle " Richard Henderson
2026-08-12 7:17 ` Philippe Mathieu-Daudé
2026-08-12 8:46 ` Alex Bennée
2026-08-12 0:31 ` [PATCH 3/7] util/cpuinfo-aarch64: Detect FEAT_CSSC Richard Henderson
2026-08-12 3:35 ` Brad Smith
2026-08-12 13:56 ` Richard Henderson
2026-08-12 0:31 ` [PATCH 4/7] tcg/aarch64: Implement min/max with FEAT_CSSC Richard Henderson
2026-08-12 7:15 ` Philippe Mathieu-Daudé
2026-08-12 0:31 ` [PATCH 5/7] target/riscv64: Implement min/max with Zbb Richard Henderson
2026-08-12 0:31 ` [PATCH 6/7] tcg/aarch64: Implement ctpop with FEAT_CSSC Richard Henderson
2026-08-12 6:59 ` Philippe Mathieu-Daudé
2026-08-12 0:31 ` [PATCH 7/7] tcg/aarch64: Use CTZ from FEAT_CSSC Richard Henderson
2026-08-12 7:06 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87tsoz20hn.fsf@draig.linaro.org \
--to=alex.bennee@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.