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Using the > FIELD_SET_FUNC action allows us to make the table itself truly constant > and move it off the stack; the RING_CMD_CCTL value is now calculated > during RTP table processing. > > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/xe/xe_hw_engine.c | 158 ++++++++++++++++++++------------------ > 1 file changed, 82 insertions(+), 76 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c > index 0b688b851b71..987cd1a49f03 100644 > --- a/drivers/gpu/drm/xe/xe_hw_engine.c > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c > @@ -387,86 +387,92 @@ void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe) > xe_tuning_process_lrc(hwe); > } > > +/* > + * RING_CMD_CCTL specifies the default MOCS entry that will be > + * used by the command streamer when executing commands that > + * don't have a way to explicitly specify a MOCS setting. > + * The default should usually reference whichever MOCS entry > + * corresponds to uncached behavior, although use of a WB cached > + * entry is recommended by the spec in certain circumstances on > + * specific platforms. > + * Bspec: 72161 > + */ > +static u32 ring_cmd_cctl_val(struct xe_gt *gt, struct xe_hw_engine *hwe) > +{ > + struct xe_device *xe = gt_to_xe(gt); > + u8 mocs_read_idx = gt->mocs.uc_index; > + > + if (hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) && > + (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)) > + mocs_read_idx = gt->mocs.wb_index; > + > + return REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, gt->mocs.uc_index) | > + REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx); > +} > + > +const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR( With the addition of the "static" keyword for engine_sr, Reviewed-by: Gustavo Sousa > + { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"), > + XE_RTP_RULES(FUNC(xe_rtp_match_always)), > + XE_RTP_ACTIONS(FIELD_SET_FUNC(RING_CMD_CCTL(0), > + CMD_CCTL_WRITE_OVERRIDE_MASK | > + CMD_CCTL_READ_OVERRIDE_MASK, > + ring_cmd_cctl_val, > + XE_RTP_ACTION_FLAG(ENGINE_BASE))) > + }, > + { XE_RTP_NAME("Disable HW status page updates for interrupts"), > + XE_RTP_RULES(FUNC(xe_rtp_match_always)), > + XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0, > + XE_RTP_ACTION_FLAG(ENGINE_BASE))) > + }, > + { XE_RTP_NAME("Disable engine 'legacy' mode"), > + XE_RTP_RULES(FUNC(xe_rtp_match_always)), > + XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE, > + XE_RTP_ACTION_FLAG(ENGINE_BASE))) > + }, > + /* > + * To allow the GSC engine to go idle on MTL we need to enable > + * idle messaging and set the hysteresis value (we use 0xA=5us > + * as recommended in spec). On platforms after MTL this is > + * enabled by default. > + */ > + { XE_RTP_NAME("MTL GSCCS IDLE MSG enable"), > + XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)), > + XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0), > + IDLE_MSG_DISABLE, > + XE_RTP_ACTION_FLAG(ENGINE_BASE)), > + FIELD_SET(RING_PWRCTX_MAXCNT(0), > + IDLE_WAIT_TIME, > + 0xA, > + XE_RTP_ACTION_FLAG(ENGINE_BASE))) > + }, > + /* Enable Priority Mem Read */ > + { XE_RTP_NAME("Priority_Mem_Read"), > + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), > + XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ, > + XE_RTP_ACTION_FLAG(ENGINE_BASE))) > + }, > + { XE_RTP_NAME("Enable CCS Engine(s)"), > + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED), > + FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE)) > + }, > + /* Use Fixed slice CCS mode */ > + { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"), > + XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)), > + XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE, > + RCU_MODE_FIXED_SLICE_CCS_MODE)) > + }, > + { XE_RTP_NAME("Enable MSI-X interrupt support"), > + XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)), > + XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE, > + XE_RTP_ACTION_FLAG(ENGINE_BASE))) > + }, > +); > + > static void > hw_engine_setup_default_state(struct xe_hw_engine *hwe) > { > - struct xe_gt *gt = hwe->gt; > - struct xe_device *xe = gt_to_xe(gt); > - /* > - * RING_CMD_CCTL specifies the default MOCS entry that will be > - * used by the command streamer when executing commands that > - * don't have a way to explicitly specify a MOCS setting. > - * The default should usually reference whichever MOCS entry > - * corresponds to uncached behavior, although use of a WB cached > - * entry is recommended by the spec in certain circumstances on > - * specific platforms. > - * Bspec: 72161 > - */ > - const u8 mocs_write_idx = gt->mocs.uc_index; > - const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) && > - (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ? > - gt->mocs.wb_index : gt->mocs.uc_index; > - u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) | > - REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx); > struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); > - const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR( > - { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"), > - XE_RTP_RULES(FUNC(xe_rtp_match_always)), > - XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0), > - CMD_CCTL_WRITE_OVERRIDE_MASK | > - CMD_CCTL_READ_OVERRIDE_MASK, > - ring_cmd_cctl_val, > - XE_RTP_ACTION_FLAG(ENGINE_BASE))) > - }, > - { XE_RTP_NAME("Disable HW status page updates for interrupts"), > - XE_RTP_RULES(FUNC(xe_rtp_match_always)), > - XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0, > - XE_RTP_ACTION_FLAG(ENGINE_BASE))) > - }, > - { XE_RTP_NAME("Disable engine 'legacy' mode"), > - XE_RTP_RULES(FUNC(xe_rtp_match_always)), > - XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE, > - XE_RTP_ACTION_FLAG(ENGINE_BASE))) > - }, > - /* > - * To allow the GSC engine to go idle on MTL we need to enable > - * idle messaging and set the hysteresis value (we use 0xA=5us > - * as recommended in spec). On platforms after MTL this is > - * enabled by default. > - */ > - { XE_RTP_NAME("MTL GSCCS IDLE MSG enable"), > - XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)), > - XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0), > - IDLE_MSG_DISABLE, > - XE_RTP_ACTION_FLAG(ENGINE_BASE)), > - FIELD_SET(RING_PWRCTX_MAXCNT(0), > - IDLE_WAIT_TIME, > - 0xA, > - XE_RTP_ACTION_FLAG(ENGINE_BASE))) > - }, > - /* Enable Priority Mem Read */ > - { XE_RTP_NAME("Priority_Mem_Read"), > - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), > - XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ, > - XE_RTP_ACTION_FLAG(ENGINE_BASE))) > - }, > - { XE_RTP_NAME("Enable CCS Engine(s)"), > - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED), > - FUNC(xe_rtp_match_first_render_or_compute)), > - XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE)) > - }, > - /* Use Fixed slice CCS mode */ > - { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"), > - XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)), > - XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE, > - RCU_MODE_FIXED_SLICE_CCS_MODE)) > - }, > - { XE_RTP_NAME("Enable MSI-X interrupt support"), > - XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)), > - XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE, > - XE_RTP_ACTION_FLAG(ENGINE_BASE))) > - }, > - ); > > xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false); > } > > -- > 2.54.0