From: Thomas Gleixner <tglx@linutronix.de>
To: Mitchell Levy via B4 Relay
<devnull+levymitchell0.gmail.com@kernel.org>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Kan Liang <kan.liang@linux.intel.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>
Cc: stable@vger.kernel.org, Borislav Petkov <bp@suse.de>,
linux-kernel@vger.kernel.org, Dave Hansen <dave.hansen@intel.com>,
Mitchell Levy <levymitchell0@gmail.com>
Subject: Re: [PATCH v2] x86/fpu: Avoid writing LBR bit to IA32_XSS unless supported
Date: Sun, 11 Aug 2024 01:08:18 +0200 [thread overview]
Message-ID: <87ttfsrn6l.ffs@tglx> (raw)
In-Reply-To: <20240809-xsave-lbr-fix-v2-1-04296b387380@gmail.com>
On Fri, Aug 09 2024 at 13:53, Mitchell Levy via wrote:
> From: Mitchell Levy <levymitchell0@gmail.com>
...
> Signed-off-by: Mitchell Levy <levymitchell0@gmail.com>
> ---
> Changes in v2:
> - Corrected Fixes tag (thanks tglx)
> - Properly check for XSAVES support of LBR (thanks tglx)
IOW. I provided you the proper fix and now you are reposting it and
claiming authorship for it?
May I ask you to read Documentation/process/ ?
Thanks,
tglx
next prev parent reply other threads:[~2024-08-10 23:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-09 20:53 [PATCH v2] x86/fpu: Avoid writing LBR bit to IA32_XSS unless supported Mitchell Levy
2024-08-09 20:53 ` Mitchell Levy via B4 Relay
2024-08-10 23:08 ` Thomas Gleixner [this message]
2024-08-11 0:30 ` Mitchell Levy
2024-08-11 7:50 ` Thomas Gleixner
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