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Fri, 4 Feb 2022 15:46:43 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 60E2EAC066; Fri, 4 Feb 2022 15:46:42 +0000 (GMT) Received: from localhost (unknown [9.211.79.16]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTPS; Fri, 4 Feb 2022 15:46:41 +0000 (GMT) From: Fabiano Rosas To: BALATON Zoltan Subject: Re: [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup In-Reply-To: <4bb49bac-12a7-b3ae-e719-e257366d15d5@eik.bme.hu> References: <20220203200957.1434641-1-farosas@linux.ibm.com> <20220203200957.1434641-11-farosas@linux.ibm.com> <4bb49bac-12a7-b3ae-e719-e257366d15d5@eik.bme.hu> Date: Fri, 04 Feb 2022 12:46:39 -0300 Message-ID: <87tude8wio.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: IV_qFF1phFhEQJmT0iJag9eIDIjSf_0K X-Proofpoint-ORIG-GUID: v2u69UkIihqkXcRC78_UsT8Rt0rkmEfu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-04_06,2022-02-03_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 spamscore=0 bulkscore=0 mlxlogscore=922 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2202040086 Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" BALATON Zoltan writes: > On Thu, 3 Feb 2022, Fabiano Rosas wrote: >> This code applies only to the 6xx CPUs, so we can remove the switch >> statement. >> >> Signed-off-by: Fabiano Rosas >> --- >> target/ppc/excp_helper.c | 31 +++++++++++-------------------- >> 1 file changed, 11 insertions(+), 20 deletions(-) >> >> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c >> index 538905c4dd..80168355bd 100644 >> --- a/target/ppc/excp_helper.c >> +++ b/target/ppc/excp_helper.c >> @@ -553,7 +553,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) >> { >> CPUState *cs = CPU(cpu); >> CPUPPCState *env = &cpu->env; >> - int excp_model = env->excp_model; >> target_ulong msr, new_msr, vector; >> int srr0, srr1; >> >> @@ -695,26 +694,18 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) >> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ >> case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ >> case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ >> - switch (excp_model) { >> - case POWERPC_EXCP_6xx: >> - /* Swap temporary saved registers with GPRs */ >> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { >> - new_msr |= (target_ulong)1 << MSR_TGPR; >> - hreg_swap_gpr_tgpr(env); >> - } >> - /* fall through */ >> - case POWERPC_EXCP_7x5: >> - ppc_excp_debug_sw_tlb(env, excp); >> - >> - msr |= env->crf[0] << 28; >> - msr |= env->error_code; /* key, D/I, S/L bits */ >> - /* Set way using a LRU mechanism */ >> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; >> - break; >> - default: >> - cpu_abort(cs, "Invalid TLB miss exception\n"); >> - break; >> + /* Swap temporary saved registers with GPRs */ >> + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { >> + new_msr |= (target_ulong)1 << MSR_TGPR; >> + hreg_swap_gpr_tgpr(env); > > I get this one... > >> } >> + >> + ppc_excp_debug_sw_tlb(env, excp); >> + >> + msr |= env->crf[0] << 28; >> + msr |= env->error_code; /* key, D/I, S/L bits */ >> + /* Set way using a LRU mechanism */ >> + msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; > > ...but not why this can be moved out from case or if. Is POWERPC_EXCP_7x5 > the same as POWERPC_EXCP_6xx now? There is a fallthrough in the original code after the first block. So POWERPC_EXCP_6xx does the TGPR work and then falls through to the debug print and SRR1 setting.