From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH for-5.0] tcg/i386: Fix %r12 guest_base initialization
Date: Mon, 06 Apr 2020 19:13:26 +0100 [thread overview]
Message-ID: <87tv1wa3eh.fsf@linaro.org> (raw)
In-Reply-To: <20200406174803.8192-1-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> When %gs cannot be used, we use register offset addressing.
> This path is almost never used, so it was clearly not tested.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> tcg/i386/tcg-target.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
> index 7f61eeedd0..ec083bddcf 100644
> --- a/tcg/i386/tcg-target.inc.c
> +++ b/tcg/i386/tcg-target.inc.c
> @@ -3737,7 +3737,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
> } else {
> /* Choose R12 because, as a base, it requires a SIB byte. */
> x86_guest_base_index = TCG_REG_R12;
> - tcg_out_mov(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);
> + tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);
> tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index);
> }
> }
--
Alex Bennée
prev parent reply other threads:[~2020-04-06 18:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-06 17:48 [PATCH for-5.0] tcg/i386: Fix %r12 guest_base initialization Richard Henderson
2020-04-06 18:13 ` Alex Bennée [this message]
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