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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t 2/4] tools/intel_reg: Support 8 and 16 bit mmio registers
Date: Mon, 09 Mar 2020 10:03:35 +0200	[thread overview]
Message-ID: <87tv2ylzu0.fsf@intel.com> (raw)
In-Reply-To: <20200306125002.21316-2-ville.syrjala@linux.intel.com>

On Fri, 06 Mar 2020, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add new "ports" for doing 8 and 16 bit mmio accesses.

Might mention the mmio-vga -> mmio8 and portio-vga -> portio port name
changes here.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_reg.c      | 53 ++++++++++++++++++++++++++++++------------
>  tools/intel_reg_spec.c | 19 +++++++++------
>  tools/intel_reg_spec.h |  8 ++++---
>  3 files changed, 55 insertions(+), 25 deletions(-)
>
> diff --git a/tools/intel_reg.c b/tools/intel_reg.c
> index 5f1beba4a269..7f8ddbd8e927 100644
> --- a/tools/intel_reg.c
> +++ b/tools/intel_reg.c
> @@ -179,6 +179,18 @@ static void to_binary(char *buf, size_t buflen, uint32_t val)
>  	snprintf(buf, buflen, "\n");
>  }
>  
> +static bool port_is_mmio(enum port_addr port)
> +{
> +	switch (port) {
> +	case PORT_MMIO_32:
> +	case PORT_MMIO_16:
> +	case PORT_MMIO_8:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
>  static void dump_decode(struct config *config, struct reg *reg, uint32_t val)
>  {
>  	char decode[1300];
> @@ -207,7 +219,7 @@ static void dump_decode(struct config *config, struct reg *reg, uint32_t val)
>  		snprintf(decode, sizeof(decode), "\n");
>  	}
>  
> -	if (reg->port_desc.port == PORT_MMIO) {
> +	if (port_is_mmio(reg->port_desc.port)) {
>  		/* Omit port name for MMIO, optionally include MMIO offset. */
>  		if (reg->mmio_offset)
>  			printf("%24s (0x%08x:0x%08x): 0x%08x%s",
> @@ -359,20 +371,23 @@ static int read_register(struct config *config, struct reg *reg, uint32_t *valp)
>  	uint32_t val = 0;
>  
>  	switch (reg->port_desc.port) {
> -	case PORT_MMIO:
> +	case PORT_MMIO_32:
>  		if (reg->engine)
>  			val = register_srm(config, reg, NULL);
>  		else
>  			val = INREG(reg->mmio_offset + reg->addr);
>  		break;
> -	case PORT_PORTIO_VGA:
> +	case PORT_MMIO_16:
> +		val = INREG16(reg->mmio_offset + reg->addr);
> +		break;
> +	case PORT_MMIO_8:
> +		val = INREG8(reg->mmio_offset + reg->addr);
> +		break;
> +	case PORT_PORTIO:
>  		iopl(3);
>  		val = inb(reg->addr);
>  		iopl(0);
>  		break;
> -	case PORT_MMIO_VGA:
> -		val = INREG8(reg->addr);
> -		break;
>  	case PORT_BUNIT:
>  	case PORT_PUNIT:
>  	case PORT_NC:
> @@ -419,30 +434,38 @@ static int write_register(struct config *config, struct reg *reg, uint32_t val)
>  	}
>  
>  	switch (reg->port_desc.port) {
> -	case PORT_MMIO:
> +	case PORT_MMIO_32:
>  		if (reg->engine) {
>  			register_srm(config, reg, &val);
>  		} else {
>  			OUTREG(reg->mmio_offset + reg->addr, val);
>  		}
>  		break;
> -	case PORT_PORTIO_VGA:
> +	case PORT_MMIO_16:
> +		if (val > 0xffff) {
> +			fprintf(stderr, "value 0x%08x out of range for port %s\n",
> +				val, reg->port_desc.name);
> +			return -1;
> +		}
> +		OUTREG16(reg->mmio_offset + reg->addr, val);
> +		break;
> +	case PORT_MMIO_8:
>  		if (val > 0xff) {
>  			fprintf(stderr, "value 0x%08x out of range for port %s\n",
>  				val, reg->port_desc.name);
>  			return -1;
>  		}
> -		iopl(3);
> -		outb(val, reg->addr);
> -		iopl(0);
> +		OUTREG8(reg->mmio_offset + reg->addr, val);
>  		break;
> -	case PORT_MMIO_VGA:
> +	case PORT_PORTIO:
>  		if (val > 0xff) {
>  			fprintf(stderr, "value 0x%08x out of range for port %s\n",
>  				val, reg->port_desc.name);
>  			return -1;
>  		}
> -		OUTREG8(reg->addr, val);
> +		iopl(3);
> +		outb(val, reg->addr);
> +		iopl(0);
>  		break;
>  	case PORT_BUNIT:
>  	case PORT_PUNIT:
> @@ -482,7 +505,7 @@ static int parse_engine(struct reg *reg, const char *s)
>  
>  	e = find_engine(s);
>  	if (e) {
> -		reg->port_desc.port = PORT_MMIO;
> +		reg->port_desc.port = PORT_MMIO_32;
>  		reg->port_desc.name = strdup(s);
>  		reg->port_desc.stride = 4;
>  		reg->engine = strdup(s);
> @@ -629,7 +652,7 @@ static int intel_reg_dump(struct config *config, int argc, char *argv[])
>  		reg = &config->regs[i];
>  
>  		/* can't dump sideband with mmiofile */
> -		if (config->mmiofile && reg->port_desc.port != PORT_MMIO)
> +		if (config->mmiofile && !port_is_mmio(reg->port_desc.port))
>  			continue;
>  
>  		dump_register(config, &config->regs[i]);
> diff --git a/tools/intel_reg_spec.c b/tools/intel_reg_spec.c
> index 5ab56ec1a31f..7c1c6ed34a9e 100644
> --- a/tools/intel_reg_spec.c
> +++ b/tools/intel_reg_spec.c
> @@ -35,17 +35,22 @@
>  static const struct port_desc port_descs[] = {
>  	{
>  		.name = "mmio",
> -		.port = PORT_MMIO,
> +		.port = PORT_MMIO_32,
>  		.stride = 4,
>  	},
>  	{
> -		.name = "portio-vga",
> -		.port = PORT_PORTIO_VGA,
> +		.name = "mmio16",
> +		.port = PORT_MMIO_16,
> +		.stride = 2,
> +	},
> +	{
> +		.name = "mmio8",
> +		.port = PORT_MMIO_8,
>  		.stride = 1,
>  	},
>  	{
> -		.name = "mmio-vga",
> -		.port = PORT_MMIO_VGA,
> +		.name = "portio",
> +		.port = PORT_PORTIO,
>  		.stride = 1,
>  	},
>  	{
> @@ -116,7 +121,7 @@ int parse_port_desc(struct reg *reg, const char *s)
>  		if (endp > s && *endp == 0) {
>  			if (n > PORT_MAX) {
>  				/* Not a sideband port, assume MMIO offset. */
> -				port = PORT_MMIO;
> +				port = PORT_MMIO_32;
>  				reg->mmio_offset = n;
>  			} else {
>  				port = n;
> @@ -127,7 +132,7 @@ int parse_port_desc(struct reg *reg, const char *s)
>  		}
>  	} else {
>  		/* No port, default to searching for MMIO. */
> -		port = PORT_MMIO;
> +		port = PORT_MMIO_32;
>  		reg->mmio_offset = 0;
>  	}
>  
> diff --git a/tools/intel_reg_spec.h b/tools/intel_reg_spec.h
> index a6e0514387df..29f4d9ae2a47 100644
> --- a/tools/intel_reg_spec.h
> +++ b/tools/intel_reg_spec.h
> @@ -25,9 +25,11 @@
>  #define __INTEL_REG_SPEC_H__
>  
>  enum port_addr {
> -	PORT_MMIO = -127,
> -	PORT_PORTIO_VGA,	/* see vga reg read/write */
> -	PORT_MMIO_VGA,		/* see vga reg read/write */
> +	PORT_MMIO_32 = -127,
> +	PORT_MMIO_16,
> +	PORT_MMIO_8,
> +
> +	PORT_PORTIO,
>  
>  	PORT_NONE = 0,

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

  reply	other threads:[~2020-03-09  8:03 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-06 12:49 [igt-dev] [PATCH i-g-t 1/4] tools/intel_reg: Simplify negative ports Ville Syrjala
2020-03-06 12:50 ` [igt-dev] [PATCH i-g-t 2/4] tools/intel_reg: Support 8 and 16 bit mmio registers Ville Syrjala
2020-03-09  8:03   ` Jani Nikula [this message]
2020-03-06 12:50 ` [igt-dev] [PATCH i-g-t 3/4] tools/intel_reg: Add support for register access via the MCHBAR mirror Ville Syrjala
2020-03-09  8:24   ` Jani Nikula
2020-03-06 12:50 ` [igt-dev] [PATCH i-g-t 4/4] tools/intel_reg: Add support for reading indexed VGA registers Ville Syrjala
2020-03-06 13:38 ` [igt-dev] ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/4] tools/intel_reg: Simplify negative ports Patchwork
2020-03-09  7:52 ` [igt-dev] [PATCH i-g-t 1/4] " Jani Nikula
  -- strict thread matches above, loose matches on Subject: below --
2023-01-25  5:42 Ville Syrjala
2023-01-25  5:42 ` [igt-dev] [PATCH i-g-t 2/4] tools/intel_reg: Support 8 and 16 bit mmio registers Ville Syrjala

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