From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:50010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hFgXn-0003kI-5E for qemu-devel@nongnu.org; Sun, 14 Apr 2019 10:55:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hFgXm-0007Bs-69 for qemu-devel@nongnu.org; Sun, 14 Apr 2019 10:55:43 -0400 Received: from mail03.asahi-net.or.jp ([202.224.55.15]:37292) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hFgXl-0007A1-Rm for qemu-devel@nongnu.org; Sun, 14 Apr 2019 10:55:42 -0400 Date: Sun, 14 Apr 2019 23:55:32 +0900 Message-ID: <87tvf0d4bf.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato In-Reply-To: <09399349-5134-7347-b86d-d28c9fd1803d@redhat.com> References: <20190325090047.122981-1-ysato@users.sourceforge.jp> <20190401140318.80498-1-ysato@users.sourceforge.jp> <20190401140318.80498-13-ysato@users.sourceforge.jp> <09399349-5134-7347-b86d-d28c9fd1803d@redhat.com> MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org On Thu, 11 Apr 2019 19:09:38 +0900, Philippe Mathieu-Daud=E9 wrote: >=20 > Hi Yoshinori, >=20 > Note about the patch subject: > - typo in regiserfields (missing 't') -> registerfields > - I'd simply use "hw/registerfields: Add 8bit and 16bit register macros" OK. > On 4/1/19 4:03 PM, Yoshinori Sato wrote: > > Some RX peripheral using 8bit and 16bit registers. > > Added 8bit and 16bit APIs. > >=20 > > Signed-off-by: Yoshinori Sato > > --- > > include/hw/registerfields.h | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > >=20 > > diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h > > index 2659a58737..f6bf911990 100644 > > --- a/include/hw/registerfields.h > > +++ b/include/hw/registerfields.h > > @@ -22,6 +22,14 @@ > > enum { A_ ## reg =3D (addr) }; = \ > > enum { R_ ## reg =3D (addr) / 4 }; > > =20 > > +#define REG8(reg, addr) = \ > > + enum { A_ ## reg =3D (addr) }; = \ > > + enum { R_ ## reg =3D (addr) }; > > + > > +#define REG16(reg, addr) = \ > > + enum { A_ ## reg =3D (addr) }; = \ > > + enum { R_ ## reg =3D (addr) / 2 }; > > + > > /* Define SHIFT, LENGTH and MASK constants for a field within a regist= er */ > > =20 > > /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BA= R_LENGTH > > @@ -40,6 +48,8 @@ > > #define FIELD_EX64(storage, reg, field) = \ > > extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ > > R_ ## reg ## _ ## field ## _LENGTH) > > +#define FIELD_EX8 FIELD_EX32 > > +#define FIELD_EX16 FIELD_EX32 > > =20 > > /* Extract a field from an array of registers */ > > #define ARRAY_FIELD_EX32(regs, reg, field) = \ >=20 > For completeness, what about adding FIELD_DP8() and FIELD_DP16()? I did not add it because I did not use it. Certainly it is strange that there is no these, so I will add it. As the registerfields support is incomplete, we will fix it together. > Regards, >=20 > Phil. >=20 --=20 Yosinori Sato From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04BB4C10F13 for ; Sun, 14 Apr 2019 14:57:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB9FC20693 for ; Sun, 14 Apr 2019 14:56:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BB9FC20693 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([127.0.0.1]:36578 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hFgZ0-0004tg-Nh for qemu-devel@archiver.kernel.org; Sun, 14 Apr 2019 10:56:58 -0400 Received: from eggs.gnu.org ([209.51.188.92]:50010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hFgXn-0003kI-5E for qemu-devel@nongnu.org; Sun, 14 Apr 2019 10:55:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hFgXm-0007Bs-69 for qemu-devel@nongnu.org; Sun, 14 Apr 2019 10:55:43 -0400 Received: from mail03.asahi-net.or.jp ([202.224.55.15]:37292) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hFgXl-0007A1-Rm for qemu-devel@nongnu.org; Sun, 14 Apr 2019 10:55:42 -0400 Received: from h61-195-96-97.vps.ablenet.jp (h61-195-96-97.vps.ablenet.jp [61.195.96.97]) (Authenticated sender: PQ4Y-STU) by mail03.asahi-net.or.jp (Postfix) with ESMTPA id CED083BDA3; Sun, 14 Apr 2019 23:55:36 +0900 (JST) Received: from yo-satoh-debian.ysato.ml (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by h61-195-96-97.vps.ablenet.jp (Postfix) with ESMTPSA id EE780240082; Sun, 14 Apr 2019 23:55:35 +0900 (JST) Date: Sun, 14 Apr 2019 23:55:32 +0900 Message-ID: <87tvf0d4bf.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= In-Reply-To: <09399349-5134-7347-b86d-d28c9fd1803d@redhat.com> References: <20190325090047.122981-1-ysato@users.sourceforge.jp> <20190401140318.80498-1-ysato@users.sourceforge.jp> <20190401140318.80498-13-ysato@users.sourceforge.jp> <09399349-5134-7347-b86d-d28c9fd1803d@redhat.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 202.224.55.15 Subject: Re: [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Message-ID: <20190414145532.rIkjDlzpR_eP2iwoNR1kMulzkG3kBfJmAWcyv116tXY@z> On Thu, 11 Apr 2019 19:09:38 +0900, Philippe Mathieu-Daud=E9 wrote: >=20 > Hi Yoshinori, >=20 > Note about the patch subject: > - typo in regiserfields (missing 't') -> registerfields > - I'd simply use "hw/registerfields: Add 8bit and 16bit register macros" OK. > On 4/1/19 4:03 PM, Yoshinori Sato wrote: > > Some RX peripheral using 8bit and 16bit registers. > > Added 8bit and 16bit APIs. > >=20 > > Signed-off-by: Yoshinori Sato > > --- > > include/hw/registerfields.h | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > >=20 > > diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h > > index 2659a58737..f6bf911990 100644 > > --- a/include/hw/registerfields.h > > +++ b/include/hw/registerfields.h > > @@ -22,6 +22,14 @@ > > enum { A_ ## reg =3D (addr) }; = \ > > enum { R_ ## reg =3D (addr) / 4 }; > > =20 > > +#define REG8(reg, addr) = \ > > + enum { A_ ## reg =3D (addr) }; = \ > > + enum { R_ ## reg =3D (addr) }; > > + > > +#define REG16(reg, addr) = \ > > + enum { A_ ## reg =3D (addr) }; = \ > > + enum { R_ ## reg =3D (addr) / 2 }; > > + > > /* Define SHIFT, LENGTH and MASK constants for a field within a regist= er */ > > =20 > > /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BA= R_LENGTH > > @@ -40,6 +48,8 @@ > > #define FIELD_EX64(storage, reg, field) = \ > > extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ > > R_ ## reg ## _ ## field ## _LENGTH) > > +#define FIELD_EX8 FIELD_EX32 > > +#define FIELD_EX16 FIELD_EX32 > > =20 > > /* Extract a field from an array of registers */ > > #define ARRAY_FIELD_EX32(regs, reg, field) = \ >=20 > For completeness, what about adding FIELD_DP8() and FIELD_DP16()? I did not add it because I did not use it. Certainly it is strange that there is no these, so I will add it. As the registerfields support is incomplete, we will fix it together. > Regards, >=20 > Phil. >=20 --=20 Yosinori Sato