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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
Subject: Re: [PATCH 6/7] drm/i915: Restart RPS using the same RP_CONTROL as from initialisation
Date: Mon, 20 Feb 2017 16:40:47 +0200	[thread overview]
Message-ID: <87tw7pc4cw.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20170220094713.22874-6-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> During initialisation, we set different flags for different
> architectures - these should be preserved when we reload the RPS
> thresholds. If we use a mmio read, it will first ensure that the
> threshold registers are written before we apply the latch in RP_CONTROL.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: stable@vger.kernel.org

This will change how the valleyview will do the DOWN_IDLE,
due to readback you will get a GEN6_RP_DOWN_IDLE_CONT.

I can't think of why we would like to keep that behaviour
as the IDLE_CONT setup is a twart in my opinion.

If you agree with the above, substitute the IDLE_CONT in
valleview setup and you can add,

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3041cd4988a6..d37e95b3525d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4884,13 +4884,9 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
>  		      GT_INTERVAL_FROM_US(dev_priv,
>  					  ei_down * threshold_down / 100));
>  
> +	/* Restart RPS to reload the thresholds */
>  	I915_WRITE_FW(GEN6_RP_CONTROL,
> -		      GEN6_RP_MEDIA_TURBO |
> -		      GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -		      GEN6_RP_MEDIA_IS_GFX |
> -		      GEN6_RP_ENABLE |
> -		      GEN6_RP_UP_BUSY_AVG |
> -		      GEN6_RP_DOWN_IDLE_AVG);
> +		      I915_READ_FW(GEN6_RP_CONTROL) | GEN6_RP_ENABLE);
>  
>  	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
>  	spin_unlock_irq(&dev_priv->uncore.lock);
> -- 
> 2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>, stable@vger.kernel.org
Subject: Re: [PATCH 6/7] drm/i915: Restart RPS using the same RP_CONTROL as from initialisation
Date: Mon, 20 Feb 2017 16:40:47 +0200	[thread overview]
Message-ID: <87tw7pc4cw.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20170220094713.22874-6-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> During initialisation, we set different flags for different
> architectures - these should be preserved when we reload the RPS
> thresholds. If we use a mmio read, it will first ensure that the
> threshold registers are written before we apply the latch in RP_CONTROL.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: stable@vger.kernel.org

This will change how the valleyview will do the DOWN_IDLE,
due to readback you will get a GEN6_RP_DOWN_IDLE_CONT.

I can't think of why we would like to keep that behaviour
as the IDLE_CONT setup is a twart in my opinion.

If you agree with the above, substitute the IDLE_CONT in
valleview setup and you can add,

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3041cd4988a6..d37e95b3525d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4884,13 +4884,9 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
>  		      GT_INTERVAL_FROM_US(dev_priv,
>  					  ei_down * threshold_down / 100));
>  
> +	/* Restart RPS to reload the thresholds */
>  	I915_WRITE_FW(GEN6_RP_CONTROL,
> -		      GEN6_RP_MEDIA_TURBO |
> -		      GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -		      GEN6_RP_MEDIA_IS_GFX |
> -		      GEN6_RP_ENABLE |
> -		      GEN6_RP_UP_BUSY_AVG |
> -		      GEN6_RP_DOWN_IDLE_AVG);
> +		      I915_READ_FW(GEN6_RP_CONTROL) | GEN6_RP_ENABLE);
>  
>  	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
>  	spin_unlock_irq(&dev_priv->uncore.lock);
> -- 
> 2.11.0

  parent reply	other threads:[~2017-02-20 14:42 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-20  9:47 [PATCH 1/7] drm/i915: Move the common RPS warnings to intel_set_rps() Chris Wilson
2017-02-20  9:47 ` [PATCH 2/7] drm/i915: Store the requested frequency whilst RPS is disabled Chris Wilson
2017-02-20 12:36   ` Szwichtenberg, Radoslaw
2017-02-20  9:47 ` [PATCH 3/7] drm/i915: Remove unrequired POSTING_READ from gen6_set_rps() Chris Wilson
2017-02-20 11:15   ` Szwichtenberg, Radoslaw
2017-02-20 12:43     ` chris
2017-02-20  9:47 ` [PATCH 4/7] drm/i915: Use set_rps to enable RPS Chris Wilson
2017-02-20  9:47   ` Chris Wilson
2017-02-20 14:29   ` Mika Kuoppala
2017-02-20 14:29     ` Mika Kuoppala
2017-02-20 14:38     ` Chris Wilson
2017-02-20  9:47 ` [PATCH 5/7] drm/i915: Take forcewake for setting the RPS thresholds Chris Wilson
2017-02-20 14:34   ` Mika Kuoppala
2017-02-20 14:34     ` Mika Kuoppala
2017-02-20 14:45     ` Chris Wilson
2017-02-20  9:47 ` [PATCH 6/7] drm/i915: Restart RPS using the same RP_CONTROL as from initialisation Chris Wilson
2017-02-20 13:33   ` Szwichtenberg, Radoslaw
2017-02-20 13:33     ` [Intel-gfx] " Szwichtenberg, Radoslaw
2017-02-20 14:40   ` Mika Kuoppala [this message]
2017-02-20 14:40     ` Mika Kuoppala
2017-02-20 14:47     ` Chris Wilson
2017-02-20 14:59       ` Mika Kuoppala
2017-02-20  9:47 ` [PATCH 7/7] drm/i915: Stop RPS as we adjust thresholds Chris Wilson
2017-02-20  9:47   ` Chris Wilson
2017-02-20 12:35   ` Szwichtenberg, Radoslaw
2017-02-20 12:35     ` [Intel-gfx] " Szwichtenberg, Radoslaw
2017-02-20 14:41   ` Mika Kuoppala
2017-02-20 14:41     ` Mika Kuoppala
2017-02-20 10:51 ` ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Move the common RPS warnings to intel_set_rps() Patchwork

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