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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Arun Siluvery <arun.siluvery@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 3/3] drm/i915/bxt: Add	WaDisablePooledEuLoadBalancingFix
Date: Fri, 03 Jun 2016 11:06:12 +0300	[thread overview]
Message-ID: <87twha1ytn.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1464932075-34466-4-git-send-email-arun.siluvery@linux.intel.com>

Arun Siluvery <arun.siluvery@linux.intel.com> writes:

> [ text/plain ]
> This is a WA affecting pooled eu which is a bxt specific feature.
>
> Cc: Winiarski, Michal <michal.winiarski@intel.com>
> Cc: Zou, Nanhai <nanhai.zou@intel.com>
> Cc: Yang, Rong R <rong.r.yang@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1d97321e..5268aed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
>  
>  #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
>  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
> +#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1<<10)
>  
>  #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
>  #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a39..a21eced 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1145,6 +1145,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  			  STALL_DOP_GATING_DISABLE);
>  
> +	/* WaDisablePooledEuLoadBalancingFix:bxt */
> +	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
> +		WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
> +				  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
> +	}
> +
>  	/* WaDisableSbeCacheDispatchPortSharing:bxt */
>  	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
>  		WA_SET_BIT_MASKED(
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2016-06-03  8:09 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-03  5:34 [PATCH v2 0/3] BXT Pooled EU kernel support and WA patches Arun Siluvery
2016-06-03  5:34 ` [PATCH v2 1/3] drm/i915:bxt: Enable Pooled EU support Arun Siluvery
2016-06-13 17:59   ` Michał Winiarski
2016-06-03  5:34 ` [PATCH v2 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6 Arun Siluvery
2016-06-03  9:20   ` Mika Kuoppala
2016-06-03 10:14   ` [PATCH v3 " Arun Siluvery
2016-06-03  5:34 ` [PATCH v2 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix Arun Siluvery
2016-06-03  8:06   ` Mika Kuoppala [this message]
2016-06-03 10:16   ` [PATCH v3 " Arun Siluvery
2016-06-03  8:23 ` ✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches Patchwork
2016-06-03 10:58 ` ✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches (rev3) Patchwork
2016-06-06  6:26   ` Arun Siluvery
2016-06-14  9:45     ` Tvrtko Ursulin

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