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b=kp9izs/C46MbG4pewZPlbPYXDXAw3u1A7/NwM/HTep0+suup6SPqDC87e4eDrdSuJV5+Uy8tlFfYMSeer9rhYQ4QgWQUA8mUdMBOcI8XLfv4KGz0r1ZAdmq3ND5sMbJ/OoQkLKiDmpeR/6PI6oPz1TafHSCKN20i8wzJFbmUhzTa02Jbs34+Qm380HpqSCt1J7M4VYjBt0bYBKPcUwZXSG1p7hklSBwCR7XlBwM9k9QEHTBNmI4ji88yePA08sYvRXS/3k6BS1WuPO2cXYgyJv6UsowtTyP85gefc+bTy9Eaf3E2IY23j+z2yPsStVS2ZPsh8wuMWEGa0XIIW9Mj5A== From: Volodymyr Babchuk To: Saman Dehghan CC: "xen-devel@lists.xenproject.org" , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Stefano Stabellini , Bertrand Marquis Subject: Re: [PATCH v4] xen/arm64: Add support Clang build on arm64 Thread-Topic: [PATCH v4] xen/arm64: Add support Clang build on arm64 Thread-Index: AQHcasii1+6T8d3E0U2GKVn8gBUvHg== Date: Tue, 7 Apr 2026 20:02:03 +0000 Message-ID: <87v7e2y1xu.fsf@epam.com> References: In-Reply-To: (Saman Dehghan's message of "Thu, 11 Dec 2025 12:04:34 -0600") Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43056d0c-dab5-4045-1752-08de94e08a01 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Apr 2026 20:02:04.1871 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: F4b7e/Ec4HV9OXQ95rDBx35uTFWRZoiV3/sIRKWq6DQGHogHhYOmQNpDjSHNYihX9phG3aeaM3f6Qf2OWU/WPE9UCuOo359alTQcnX1cLjg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7510 X-purgate-ID: tlsNG-4011c0/1775592126-0EB4D0B1-35D6F21F/0/0 X-purgate-type: clean X-purgate-size: 5667 Hi Saman, Saman Dehghan writes: > This patch enables building Xen for the arm64 using the Clang/LLVM compil= er. > Changes include: > - Add explicit -march=3Darmv8 flag for arm64 builds. > - Introduce `READ_FP_SYSREG` and `WRITE_FP_SYSREG` to encapsulate the req= uired > `.arch_extension fp` directive for system fp register access. > - Add ".arch_extension fp" to the inline assembly for `save_state` and > `restore_state`. > It breaks GCC-based build (see below) Also, are you going to address to other issues that I tried to tackle in https://patchew.org/Xen/20241129014850.2852844-1-volodymyr._5Fbabchuk@epam.= com/ ? > Signed-off-by: Saman Dehghan > --- > README | 2 ++ > xen/arch/arm/arch.mk | 1 + > xen/arch/arm/arm64/vfp.c | 34 ++++++++++++++++++++++++++-------- > 3 files changed, 29 insertions(+), 8 deletions(-) > > diff --git a/README b/README > index 889a4ea906..67c1aa7fe6 100644 > --- a/README > +++ b/README > @@ -45,6 +45,8 @@ provided by your OS distributor: > - For ARM: > - GCC 5.1 or later > - GNU Binutils 2.25 or later > + or > + - Clang/LLVM 11 or later > - For RISC-V 64-bit: > - GCC 12.2 or later > - GNU Binutils 2.39 or later > diff --git a/xen/arch/arm/arch.mk b/xen/arch/arm/arch.mk > index 9c4bedfb3b..bcf548069b 100644 > --- a/xen/arch/arm/arch.mk > +++ b/xen/arch/arm/arch.mk > @@ -13,6 +13,7 @@ ifeq ($(CONFIG_MPU),y) > CFLAGS-$(CONFIG_ARM_64) +=3D -march=3Darmv8-r > else > CFLAGS-$(CONFIG_ARM_64) +=3D -mcpu=3Dgeneric > +CFLAGS-$(CONFIG_ARM_64) +=3D -march=3Darmv8 This breaks build for me: cc1: error: unknown value 'armv8' for '-march' cc1: note: valid arguments are: armv8-a armv8.1-a armv8.2-a armv8.3-a armv8= .4-a armv8.5-a armv8.6-a armv8.7-a armv8.8-a armv8.9-a armv8-r armv9-a armv= 9.1-a armv9.2-a armv9.3-a armv9.4-a armv9.5-a; did you mean 'armv8-a'? > endif > CFLAGS-$(CONFIG_ARM_64) +=3D -mgeneral-regs-only # No fp registers etc > $(call cc-option-add,CFLAGS-$(CONFIG_ARM_64),CC,-mno-outline-atomics) > diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c > index c4f89c7b0e..cd5c97cfd0 100644 > --- a/xen/arch/arm/arm64/vfp.c > +++ b/xen/arch/arm/arm64/vfp.c > @@ -6,7 +6,8 @@ > =20 > static inline void save_state(uint64_t *fpregs) > { > - asm volatile("stp q0, q1, [%1, #16 * 0]\n\t" > + asm volatile(".arch_extension fp\n\t" > + "stp q0, q1, [%1, #16 * 0]\n\t" > "stp q2, q3, [%1, #16 * 2]\n\t" > "stp q4, q5, [%1, #16 * 4]\n\t" > "stp q6, q7, [%1, #16 * 6]\n\t" > @@ -22,12 +23,14 @@ static inline void save_state(uint64_t *fpregs) > "stp q26, q27, [%1, #16 * 26]\n\t" > "stp q28, q29, [%1, #16 * 28]\n\t" > "stp q30, q31, [%1, #16 * 30]\n\t" > + ".arch_extension nofp\n\t" > : "=3DQ" (*fpregs) : "r" (fpregs)); > } > =20 > static inline void restore_state(const uint64_t *fpregs) > { > - asm volatile("ldp q0, q1, [%1, #16 * 0]\n\t" > + asm volatile(".arch_extension fp\n\t" > + "ldp q0, q1, [%1, #16 * 0]\n\t" > "ldp q2, q3, [%1, #16 * 2]\n\t" > "ldp q4, q5, [%1, #16 * 4]\n\t" > "ldp q6, q7, [%1, #16 * 6]\n\t" > @@ -43,9 +46,24 @@ static inline void restore_state(const uint64_t *fpreg= s) > "ldp q26, q27, [%1, #16 * 26]\n\t" > "ldp q28, q29, [%1, #16 * 28]\n\t" > "ldp q30, q31, [%1, #16 * 30]\n\t" > + ".arch_extension nofp\n\t" > : : "Q" (*fpregs), "r" (fpregs)); > } > =20 > +#define WRITE_FP_SYSREG(v, name) do { \ > + uint64_t _r =3D (v); \ > + asm volatile(".arch_extension fp\n\t" \ > + "msr "__stringify(name)", %0\n\t" \ > + ".arch_extension nofp" : : "r" (_r)); \ > +} while (0) > + > +#define READ_FP_SYSREG(name) ({ \ > + uint64_t _r; \ > + asm volatile(".arch_extension fp\n\t" \ > + "mrs %0, "__stringify(name)"\n\t" \ > + ".arch_extension nofp" : "=3Dr" (_r)); \ > +_r; }) > + > void vfp_save_state(struct vcpu *v) > { > if ( !cpu_has_fp ) > @@ -56,10 +74,10 @@ void vfp_save_state(struct vcpu *v) > else > save_state(v->arch.vfp.fpregs); > =20 > - v->arch.vfp.fpsr =3D READ_SYSREG(FPSR); > - v->arch.vfp.fpcr =3D READ_SYSREG(FPCR); > + v->arch.vfp.fpsr =3D READ_FP_SYSREG(FPSR); > + v->arch.vfp.fpcr =3D READ_FP_SYSREG(FPCR); > if ( is_32bit_domain(v->domain) ) > - v->arch.vfp.fpexc32_el2 =3D READ_SYSREG(FPEXC32_EL2); > + v->arch.vfp.fpexc32_el2 =3D READ_FP_SYSREG(FPEXC32_EL2); > } > =20 > void vfp_restore_state(struct vcpu *v) > @@ -72,8 +90,8 @@ void vfp_restore_state(struct vcpu *v) > else > restore_state(v->arch.vfp.fpregs); > =20 > - WRITE_SYSREG(v->arch.vfp.fpsr, FPSR); > - WRITE_SYSREG(v->arch.vfp.fpcr, FPCR); > + WRITE_FP_SYSREG(v->arch.vfp.fpsr, FPSR); > + WRITE_FP_SYSREG(v->arch.vfp.fpcr, FPCR); > if ( is_32bit_domain(v->domain) ) > - WRITE_SYSREG(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); > + WRITE_FP_SYSREG(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); > } --=20 WBR, Volodymyr=