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Fri, 21 Mar 2025 11:29:26 -0400 X-MC-Unique: z9XOUjvyPIWnnUBBdnLNDg-1 X-Mimecast-MFC-AGG-ID: z9XOUjvyPIWnnUBBdnLNDg_1742570965 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id CAD31180AF50; Fri, 21 Mar 2025 15:29:23 +0000 (UTC) Received: from localhost (unknown [10.67.24.51]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 4C0541954B04; Fri, 21 Mar 2025 15:29:19 +0000 (UTC) From: Cornelia Huck To: Sebastian Ott Cc: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: Re: [PATCH v3 01/14] arm/cpu: Add sysreg definitions in cpu-sysregs.h In-Reply-To: <7c6ab887-2c9f-6646-4f0c-790671b28c62@redhat.com> Organization: "Red Hat GmbH, Sitz: Werner-von-Siemens-Ring 12, D-85630 Grasbrunn, Handelsregister: Amtsgericht =?utf-8?Q?M=C3=BCnchen=2C?= HRB 153243, =?utf-8?Q?Gesch=C3=A4ftsf=C3=BChrer=3A?= Ryan Barnhart, Charles Cachera, Michael O'Neill, Amy Ross" References: <20250311162824.199721-1-cohuck@redhat.com> <20250311162824.199721-2-cohuck@redhat.com> <7c6ab887-2c9f-6646-4f0c-790671b28c62@redhat.com> User-Agent: Notmuch/0.38.3 (https://notmuchmail.org) Date: Fri, 21 Mar 2025 16:29:13 +0100 Message-ID: <87v7s2tnau.fsf@redhat.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 On Thu, Mar 20 2025, Sebastian Ott wrote: > On Tue, 11 Mar 2025, Cornelia Huck wrote: >> +++ b/target/arm/cpu.h > [...] >> +/* REG is ID_XXX */ >> +#define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ >> + ({ \ >> + ARMISARegisters *i_ = (ISAR); \ >> + uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \ > > This won't work for regs that don't fit this naming scheme. Up to this > point in the series that's only CTR_EL0, later with the auto generation it > will be more. But I guess this can be extended when/if there's an actual > need.. All ID_XXX registers fit the "has an _EL1 suffix" scheme, though, and these are what we use the _IDREG() accessors for (we use FIELD_DP64 for CTR_EL0 fields.) (At least, that matches what I see called "ID registers" in the Arm Arm.) The sysregs we get via KVM_ARM_GET_REG_WRITABLE_MASKS/KVM_ARM_FEATURE_ID_RANGE contain ID_XXX registers, and some more writable registers in the feature id range which are not really id registers (but which we want to handle via the command line as well). I think all the non _EL1 registers we want to handle fall into the latter category (i.e. we're not going to use the _IDREG() accessors for them?)