From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5001DC02183 for ; Wed, 15 Jan 2025 18:54:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jU80gtX9BvYEMREk4VlyW1fhLjdqX+HGVZniBWvY4RE=; b=jJMX8GxQpaXnVK 4NiObub4BHmj6UXXE9fGXFQOjBEER8waWYfS4Y2ptBPDiEtCjLais90jmKLkYVRoDJ4qMRU675PlA JOI9nLA8GDeWz5nK2V2WNT5ymiVgftE2jsRYhO6oT3xHe7E7R5iA386uAu80gtv8CBS+GTHwKsblO ybkwTePvyMm7bQ4Q2apFpL1AtkNogZRT9MSTLhBA/kUpcxitOBD2y9RhpaNBVll8IlBjOwuVb8TkI GSQ5YH26jlTYrITq3gu9k23BCSv/S9hYaqip/6RsZKospMCb99ZMpzPd4byQlut9fV4ibkvgGBdbm WNUZk4HpgL7WIdmzwgNQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tY8XE-0000000Cpei-2OQV; Wed, 15 Jan 2025 18:54:36 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tY8XD-0000000CpeU-06p3 for linux-mtd@bombadil.infradead.org; Wed, 15 Jan 2025 18:54:35 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :MIME-Version:Message-ID:Date:References:In-Reply-To:Subject:Cc:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=dQkA5beGm5rsGRni+AoHBlCFbxyYjwSxIyvpG2TQuog=; b=TW7VGx9bCAqr05COYTabV6XKoj IYGYY+DUzb0A/iwhXr/3gaRBNYuNzNS45LaiB/05Z7QY3M96sKfauyQlgPajA7hz0gdXTn0gm2Mvd h1fTk5vz8rThC0q4vxZvZ9ZlOCHaDU0OcGyvp5I+vBB9mAUCVcb9JQr/cS5KFW4fe+7DPLxjxx4GB BybDh+g9PMKgRRo7zzK13fWeTZIohkLrQNOtb9GfHb+uZZyrZnzxIpzZO/bl3y327cpt7noj4Qwov eAD1eG5knmZIuMl/SW8lLi90yXd3cw4cwb0mLb89qPc1zdW9Wf+XPFhxbFsY5paB35Kr2uCjtxT56 kZlANI2g==; Received: from relay7-d.mail.gandi.net ([2001:4b98:dc4:8::227]) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tY8X7-0000000AuVt-1R74 for linux-mtd@lists.infradead.org; Wed, 15 Jan 2025 18:54:32 +0000 Received: by mail.gandi.net (Postfix) with ESMTPSA id B9F9D20004; Wed, 15 Jan 2025 18:54:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1736967265; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dQkA5beGm5rsGRni+AoHBlCFbxyYjwSxIyvpG2TQuog=; b=V/ngaiicgfFZCGHnAqnLEXmWdN0P32WNBk75Bx/XwZZ+DyMEP1pA6qGxXtkg324qsNXOF3 mPTpLSjYV/O0qRf4bodeTklG4P/QPw2RBG1ZnTjQfvo1o7JDqnX42RfS3XF1utjjELq04L FViT5xu7ttWp17foLc243O1EPVV2mmC+Ps9MNd7O+TKxyfO/LPbD/rwI/D8EnYa9D7TtTs piqh6avkFJyD9/EEssFKtOMUI/vrP1EWlCmPhCcGPH8fgOPcpDUe31ZtqTD/qhq2CxCFbV MY95jrYgJunQwQnFVBvGi+Xs8yHjrPdr4GMt2KwLQ+wra/KRrTo5k/cVYgVSgg== From: Miquel Raynal To: Keguang Zhang via B4 Relay Cc: Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , keguang.zhang@gmail.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Subject: Re: [PATCH v11 2/2] mtd: rawnand: Add Loongson-1 NAND Controller Driver In-Reply-To: <20241217-loongson1-nand-v11-2-b692c58988bb@gmail.com> (Keguang Zhang via's message of "Tue, 17 Dec 2024 18:16:50 +0800") References: <20241217-loongson1-nand-v11-0-b692c58988bb@gmail.com> <20241217-loongson1-nand-v11-2-b692c58988bb@gmail.com> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Wed, 15 Jan 2025 19:54:23 +0100 Message-ID: <87v7ufnc0w.fsf@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250115_185429_610716_080422D4 X-CRM114-Status: GOOD ( 22.25 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGVsbG8gS2VndWFuZywKCk9uIDE3LzEyLzIwMjQgYXQgMTg6MTY6NTAgKzA4LCBLZWd1YW5nIFpo YW5nIHZpYSBCNCBSZWxheSA8ZGV2bnVsbCtrZWd1YW5nLnpoYW5nLmdtYWlsLmNvbUBrZXJuZWwu b3JnPiB3cm90ZToKCj4gK3N0YXRpYyBpbnQgbHMxeF9uYW5kX29wX2NtZF9tYXBwaW5nKHN0cnVj dCBuYW5kX2NoaXAgKmNoaXAsIHN0cnVjdCBsczF4X25hbmRfb3AgKm9wLCB1OCBvcGNvZGUpCj4g K3sKPiArCXN0cnVjdCBsczF4X25hbmRfaG9zdCAqaG9zdCA9IG5hbmRfZ2V0X2NvbnRyb2xsZXJf ZGF0YShjaGlwKTsKPiArCWludCByZXQgPSAwOwoKVGhpcyByZXR1cm4gY29kZSBpcyB1bnVzZWQu Cgo+ICsKPiArCW9wLT5yb3dfc3RhcnQgPSBjaGlwLT5wYWdlX3NoaWZ0ICsgMTsKPiArCj4gKwkv KiBUaGUgY29udHJvbGxlciBhYnN0cmFjdHMgdGhlIGZvbGxvd2luZyBOQU5EIG9wZXJhdGlvbnMu ICovCj4gKwlzd2l0Y2ggKG9wY29kZSkgewo+ICsJY2FzZSBOQU5EX0NNRF9TVEFUVVM6Cj4gKwkJ b3AtPmNtZF9yZWcgPSBMUzFYX05BTkRfQ01EX1NUQVRVUzsKPiArCQlicmVhazsKPiArCWNhc2Ug TkFORF9DTURfUkVTRVQ6Cj4gKwkJb3AtPmNtZF9yZWcgPSBMUzFYX05BTkRfQ01EX1JFU0VUOwo+ ICsJCWJyZWFrOwo+ICsJY2FzZSBOQU5EX0NNRF9SRUFESUQ6Cj4gKwkJb3AtPmlzX3JlYWRpZCA9 IHRydWU7Cj4gKwkJb3AtPmNtZF9yZWcgPSBMUzFYX05BTkRfQ01EX1JFQURJRDsKPiArCQlicmVh azsKPiArCWNhc2UgTkFORF9DTURfRVJBU0UxOgo+ICsJCW9wLT5pc19lcmFzZSA9IHRydWU7Cj4g KwkJb3AtPmFkZHJzX29mZnNldCA9IDI7Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIE5BTkRfQ01EX0VS QVNFMjoKPiArCQlpZiAoIW9wLT5pc19lcmFzZSkKPiArCQkJcmV0dXJuIC1FT1BOT1RTVVBQOwo+ ICsJCS8qIER1cmluZyBlcmFzaW5nLCByb3dfc3RhcnQgZGlmZmVycyBmcm9tIHRoZSBkZWZhdWx0 IHZhbHVlLiAqLwoKLi4uCgo+ICtzdGF0aWMgdm9pZCBsczF4X25hbmRfdHJpZ2dlcl9vcChzdHJ1 Y3QgbHMxeF9uYW5kX2hvc3QgKmhvc3QsIHN0cnVjdCBsczF4X25hbmRfb3AgKm9wKQo+ICt7Cj4g KwlzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwID0gJmhvc3QtPmNoaXA7Cj4gKwlzdHJ1Y3QgbXRkX2lu Zm8gKm10ZCA9IG5hbmRfdG9fbXRkKGNoaXApOwo+ICsJaW50IGNvbDAgPSBvcC0+YWRkcnNbMF07 Cj4gKwlzaG9ydCBjb2w7Cj4gKwo+ICsJLyogcmVzdG9yZSByb3cgYWRkcmVzcyBmb3IgY29sdW1u IGNoYW5nZSAqLwo+ICsJaWYgKG9wLT5pc19jaGFuZ2VfY29sdW1uKSB7Cj4gKwkJb3AtPmFkZHIy X3JlZyA9IHJlYWRsKGhvc3QtPnJlZ19iYXNlICsgTFMxWF9OQU5EX0FERFIyKTsKPiArCQlvcC0+ YWRkcjFfcmVnID0gcmVhZGwoaG9zdC0+cmVnX2Jhc2UgKyBMUzFYX05BTkRfQUREUjEpOwo+ICsJ CW9wLT5hZGRyMV9yZWcgJj0gfihtdGQtPndyaXRlc2l6ZSAtIDEpOwo+ICsJfQoKVGhpcyBsb29r cyB2ZXJ5IHN1c3BpY2lvdXMuIFlvdSBzaG91bGQgbm90IGhhdmUgdG8gZG8gdGhhdCBhbmQgdG8g YmUKaG9uZXN0LCBJIGRvbid0IHVuZGVydGFuZCB3aGF0IHRoaXMgbWVhbnMuCgo+ICsKPiArCWlm ICghSVNfQUxJR05FRChjb2wwLCBjaGlwLT5idWZfYWxpZ24pKSB7Cj4gKwkJY29sMCA9IEFMSUdO X0RPV04ob3AtPmFkZHJzWzBdLCBjaGlwLT5idWZfYWxpZ24pOwo+ICsJCW9wLT5hbGlnbmVkX29m ZnNldCA9IG9wLT5hZGRyc1swXSAtIGNvbDA7Cj4gKwkJb3AtPmFkZHJzWzBdID0gY29sMDsKPiAr CX0KPiArCj4gKwlpZiAoaG9zdC0+ZGF0YS0+cGFyc2VfYWRkcmVzcykKPiArCQlob3N0LT5kYXRh LT5wYXJzZV9hZGRyZXNzKG9wKTsKPiArCj4gKwkvKiBzZXQgYWRkcmVzcyAqLwo+ICsJd3JpdGVs KG9wLT5hZGRyMV9yZWcsIGhvc3QtPnJlZ19iYXNlICsgTFMxWF9OQU5EX0FERFIxKTsKPiArCXdy aXRlbChvcC0+YWRkcjJfcmVnLCBob3N0LT5yZWdfYmFzZSArIExTMVhfTkFORF9BRERSMik7Cj4g Kwo+ICsJLyogc2V0IG9wZXJhdGlvbiBsZW5ndGggKi8KPiArCWlmIChvcC0+aXNfd3JpdGUgfHwg b3AtPmlzX3JlYWQgfHwgb3AtPmlzX2NoYW5nZV9jb2x1bW4pCj4gKwkJb3AtPmxlbiA9IEFMSUdO KG9wLT5vcmlnX2xlbiArIG9wLT5hbGlnbmVkX29mZnNldCwgY2hpcC0+YnVmX2FsaWduKTsKPiAr CWVsc2UgaWYgKG9wLT5pc19lcmFzZSkKPiArCQlvcC0+bGVuID0gMTsKPiArCWVsc2UKPiArCQlv cC0+bGVuID0gb3AtPm9yaWdfbGVuOwo+ICsKPiArCXdyaXRlbChvcC0+bGVuLCBob3N0LT5yZWdf YmFzZSArIExTMVhfTkFORF9PUF9OVU0pOwo+ICsKPiArCS8qIHNldCBvcGVyYXRpb24gYXJlYSAq Lwo+ICsJY29sID0gb3AtPmFkZHJzWzFdIDw8IEJJVFNfUEVSX0JZVEUgfCBvcC0+YWRkcnNbMF07 Cj4gKwlpZiAob3AtPm9yaWdfbGVuICYmICFvcC0+aXNfcmVhZGlkKSB7Cj4gKwkJaWYgKGNvbCA8 IG10ZC0+d3JpdGVzaXplKQo+ICsJCQlvcC0+Y21kX3JlZyB8PSBMUzFYX05BTkRfQ01EX09QX01B SU47Cj4gKwo+ICsJCW9wLT5jbWRfcmVnIHw9IExTMVhfTkFORF9DTURfT1BfU1BBUkU7Cj4gKwl9 Cj4gKwo+ICsJLyogc2V0IG9wZXJhdGlvbiBzY29wZSAqLwo+ICsJaWYgKGhvc3QtPmRhdGEtPm9w X3Njb3BlX2ZpZWxkKSB7Cj4gKwkJdW5zaWduZWQgaW50IG9wX3Njb3BlOwo+ICsKPiArCQlzd2l0 Y2ggKG9wLT5jbWRfcmVnICYgTFMxWF9OQU5EX0NNRF9PUF9BUkVBX01BU0spIHsKPiArCQljYXNl IExTMVhfTkFORF9DTURfT1BfTUFJTjoKPiArCQkJb3Bfc2NvcGUgPSBtdGQtPndyaXRlc2l6ZTsK PiArCQkJYnJlYWs7Cj4gKwkJY2FzZSBMUzFYX05BTkRfQ01EX09QX1NQQVJFOgo+ICsJCQlvcF9z Y29wZSA9IG10ZC0+b29ic2l6ZTsKPiArCQkJYnJlYWs7Cj4gKwkJY2FzZSBMUzFYX05BTkRfQ01E X09QX0FSRUFfTUFTSzoKPiArCQkJb3Bfc2NvcGUgPSBtdGQtPndyaXRlc2l6ZSArIG10ZC0+b29i c2l6ZTsKPiArCQkJYnJlYWs7Cj4gKwkJZGVmYXVsdDoKPiArCQkJb3Bfc2NvcGUgPSAwOwo+ICsJ CQlicmVhazsKPiArCQl9CgpQbGVhc2UgZ2V0IHJpZCBvZiB0aGlzIGV4dHJhIHN0ZXAuIEknbSBu b3QgYSBiaWcgZmFuIG9mIGl0LCBidXQgdGhpcyBjYW4KYmUgdmVyeSB3ZWxsIHNpbXBsaWZpZWQg YW5kIHRoaXMgd2hvbGUgc3dpdGNoIHJlbW92ZWQuCgo+ICsKPiArCQlvcF9zY29wZSA8PD0gX19m ZnMoaG9zdC0+ZGF0YS0+b3Bfc2NvcGVfZmllbGQpOwo+ICsJCXJlZ21hcF91cGRhdGVfYml0cyho b3N0LT5yZWdtYXAsIExTMVhfTkFORF9QQVJBTSwKPiArCQkJCSAgIGhvc3QtPmRhdGEtPm9wX3Nj b3BlX2ZpZWxkLCBvcF9zY29wZSk7Cj4gKwl9Cj4gKwo+ICsJLyogc2V0IGNvbW1hbmQgKi8KPiAr CXdyaXRlbChvcC0+Y21kX3JlZywgaG9zdC0+cmVnX2Jhc2UgKyBMUzFYX05BTkRfQ01EKTsKPiAr Cj4gKwkvKiB0cmlnZ2VyIG9wZXJhdGlvbiAqLwo+ICsJcmVnbWFwX3dyaXRlX2JpdHMoaG9zdC0+ cmVnbWFwLCBMUzFYX05BTkRfQ01ELCBMUzFYX05BTkRfQ01EX1ZBTElELCBMUzFYX05BTkRfQ01E X1ZBTElEKTsKPiArfQo+ICsKCi4uLgoKPiArc3RhdGljIGNvbnN0IHN0cnVjdCBuYW5kX29wX3Bh cnNlciBsczF4X25hbmRfb3BfcGFyc2VyID0gTkFORF9PUF9QQVJTRVIoCj4gKwlOQU5EX09QX1BB UlNFUl9QQVRURVJOKAo+ICsJCWxzMXhfbmFuZF9yZWFkX2lkX3R5cGVfZXhlYywKPiArCQlOQU5E X09QX1BBUlNFUl9QQVRfQ01EX0VMRU0oZmFsc2UpLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9B RERSX0VMRU0oZmFsc2UsIExTMVhfTkFORF9NQVhfQUREUl9DWUMpLAo+ICsJCU5BTkRfT1BfUEFS U0VSX1BBVF9EQVRBX0lOX0VMRU0oZmFsc2UsIDgpKSwKPiArCU5BTkRfT1BfUEFSU0VSX1BBVFRF Uk4oCj4gKwkJbHMxeF9uYW5kX3JlYWRfc3RhdHVzX3R5cGVfZXhlYywKPiArCQlOQU5EX09QX1BB UlNFUl9QQVRfQ01EX0VMRU0oZmFsc2UpLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9EQVRBX0lO X0VMRU0oZmFsc2UsIDEpKSwKPiArCU5BTkRfT1BfUEFSU0VSX1BBVFRFUk4oCj4gKwkJbHMxeF9u YW5kX3plcm9sZW5fdHlwZV9leGVjLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9DTURfRUxFTShm YWxzZSksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX1dBSVRSRFlfRUxFTShmYWxzZSkpLAo+ICsJ TkFORF9PUF9QQVJTRVJfUEFUVEVSTigKPiArCQlsczF4X25hbmRfemVyb2xlbl90eXBlX2V4ZWMs Cj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX0NNRF9FTEVNKGZhbHNlKSwKPiArCQlOQU5EX09QX1BB UlNFUl9QQVRfQUREUl9FTEVNKGZhbHNlLCBMUzFYX05BTkRfTUFYX0FERFJfQ1lDKSwKPiArCQlO QU5EX09QX1BBUlNFUl9QQVRfQ01EX0VMRU0oZmFsc2UpLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BB VF9XQUlUUkRZX0VMRU0oZmFsc2UpKSwKPiArCU5BTkRfT1BfUEFSU0VSX1BBVFRFUk4oCj4gKwkJ bHMxeF9uYW5kX2RhdGFfdHlwZV9leGVjLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9DTURfRUxF TShmYWxzZSksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX0FERFJfRUxFTShmYWxzZSwgTFMxWF9O QU5EX01BWF9BRERSX0NZQyksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX0NNRF9FTEVNKGZhbHNl KSwKPiArCQlOQU5EX09QX1BBUlNFUl9QQVRfV0FJVFJEWV9FTEVNKHRydWUpLAo+ICsJCU5BTkRf T1BfUEFSU0VSX1BBVF9EQVRBX0lOX0VMRU0oZmFsc2UsIDApKSwKPiArCU5BTkRfT1BfUEFSU0VS X1BBVFRFUk4oCj4gKwkJbHMxeF9uYW5kX2RhdGFfdHlwZV9leGVjLAo+ICsJCU5BTkRfT1BfUEFS U0VSX1BBVF9DTURfRUxFTShmYWxzZSksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX0FERFJfRUxF TShmYWxzZSwgTFMxWF9OQU5EX01BWF9BRERSX0NZQyksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFU X0RBVEFfT1VUX0VMRU0oZmFsc2UsIDApLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9DTURfRUxF TShmYWxzZSksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX1dBSVRSRFlfRUxFTSh0cnVlKSksCj4g KwkpOwo+ICsKPiArc3RhdGljIGlubGluZSBib29sIGxzMXhfbmFuZF9pc192YWxpZF9jbWQodTgg b3Bjb2RlKQo+ICt7Cj4gKwlyZXR1cm4gb3Bjb2RlID09IE5BTkRfQ01EX1JFU0VUIHx8Cj4gKwkg ICAgICAgb3Bjb2RlID09IE5BTkRfQ01EX1JFQURJRCB8fAo+ICsJICAgICAgIG9wY29kZSA9PSBO QU5EX0NNRF9FUkFTRTEgfHwKPiArCSAgICAgICBvcGNvZGUgPT0gTkFORF9DTURfRVJBU0UyIHx8 Cj4gKwkgICAgICAgb3Bjb2RlID09IE5BTkRfQ01EX1NUQVRVUyB8fAo+ICsJICAgICAgIG9wY29k ZSA9PSBOQU5EX0NNRF9TRVFJTiB8fAo+ICsJICAgICAgIG9wY29kZSA9PSBOQU5EX0NNRF9QQUdF UFJPRyB8fAo+ICsJICAgICAgIG9wY29kZSA9PSBOQU5EX0NNRF9STkRPVVQgfHwKPiArCSAgICAg ICBvcGNvZGUgPT0gTkFORF9DTURfUk5ET1VUU1RBUlQgfHwKPiArCSAgICAgICBvcGNvZGUgPT0g TkFORF9DTURfUkVBRDAgfHwKPiArCSAgICAgICBvcGNvZGUgPT0gTkFORF9DTURfUkVBRFNUQVJU Owo+ICt9Cj4gKwo+ICtzdGF0aWMgaW5saW5lIGJvb2wgbHMxeF9uYW5kX2lzX2NtZF9zZXF1ZW5j ZShjb25zdCBzdHJ1Y3QgbmFuZF9vcF9pbnN0ciAqaW5zdHIxLAo+ICsJCQkJCSAgICAgY29uc3Qg c3RydWN0IG5hbmRfb3BfaW5zdHIgKmluc3RyMikKPiArewo+ICsJcmV0dXJuIGluc3RyMS0+dHlw ZSA9PSBOQU5EX09QX0NNRF9JTlNUUiAmJiBpbnN0cjItPnR5cGUgPT0gTkFORF9PUF9DTURfSU5T VFI7Cj4gK30KPiArCj4gK3N0YXRpYyBpbmxpbmUgYm9vbCBsczF4X25hbmRfaXNfZXJhc2Vfc2Vx dWVuY2UoY29uc3Qgc3RydWN0IG5hbmRfb3BfaW5zdHIgKmluc3RyMSwKPiArCQkJCQkgICAgICAg Y29uc3Qgc3RydWN0IG5hbmRfb3BfaW5zdHIgKmluc3RyMikKPiArewo+ICsJcmV0dXJuIGluc3Ry MS0+Y3R4LmNtZC5vcGNvZGUgPT0gTkFORF9DTURfRVJBU0UxICYmCj4gKwkgICAgICAgaW5zdHIy LT5jdHguY21kLm9wY29kZSA9PSBOQU5EX0NNRF9FUkFTRTI7Cj4gK30KPiArCj4gK3N0YXRpYyBp bmxpbmUgYm9vbCBsczF4X25hbmRfaXNfd3JpdGVfc2VxdWVuY2UoY29uc3Qgc3RydWN0IG5hbmRf b3BfaW5zdHIgKmluc3RyMSwKPiArCQkJCQkgICAgICAgY29uc3Qgc3RydWN0IG5hbmRfb3BfaW5z dHIgKmluc3RyMikKPiArewo+ICsJcmV0dXJuIGluc3RyMS0+Y3R4LmNtZC5vcGNvZGUgPT0gTkFO RF9DTURfU0VRSU4gJiYKPiArCSAgICAgICBpbnN0cjItPmN0eC5jbWQub3Bjb2RlID09IE5BTkRf Q01EX1BBR0VQUk9HOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW5saW5lIGJvb2wgbHMxeF9uYW5kX2lz X3JlYWRfc2VxdWVuY2UoY29uc3Qgc3RydWN0IG5hbmRfb3BfaW5zdHIgKmluc3RyMSwKPiArCQkJ CQkgICAgICBjb25zdCBzdHJ1Y3QgbmFuZF9vcF9pbnN0ciAqaW5zdHIyKQo+ICt7Cj4gKwlyZXR1 cm4gKGluc3RyMS0+Y3R4LmNtZC5vcGNvZGUgPT0gTkFORF9DTURfUkVBRDAgJiYKPiArCQlpbnN0 cjItPmN0eC5jbWQub3Bjb2RlID09IE5BTkRfQ01EX1JFQURTVEFSVCkgfHwKPiArCSAgICAgICAo aW5zdHIxLT5jdHguY21kLm9wY29kZSA9PSBOQU5EX0NNRF9STkRPVVQgJiYKPiArCQlpbnN0cjIt PmN0eC5jbWQub3Bjb2RlID09IE5BTkRfQ01EX1JORE9VVFNUQVJUKTsKPiArfQo+ICsKPiArc3Rh dGljIGludCBsczF4X25hbmRfY2hlY2tfb3Aoc3RydWN0IG5hbmRfY2hpcCAqY2hpcCwgY29uc3Qg c3RydWN0IG5hbmRfb3BlcmF0aW9uICpvcCkKPiArewo+ICsJY29uc3Qgc3RydWN0IG5hbmRfb3Bf aW5zdHIgKmluc3RyOwo+ICsJaW50IG9wX2lkOwo+ICsKPiArCWZvciAob3BfaWQgPSAwOyBvcF9p ZCA8IG9wLT5uaW5zdHJzOyBvcF9pZCsrKSB7Cj4gKwkJaW5zdHIgPSAmb3AtPmluc3Ryc1tvcF9p ZF07Cj4gKwo+ICsJCXN3aXRjaCAoaW5zdHItPnR5cGUpIHsKPiArCQljYXNlIE5BTkRfT1BfQ01E X0lOU1RSOgo+ICsJCQlpZiAoIWxzMXhfbmFuZF9pc192YWxpZF9jbWQoaW5zdHItPmN0eC5jbWQu b3Bjb2RlKSkKPiArCQkJCXJldHVybiAtRU9QTk9UU1VQUDsKPiArCQkJYnJlYWs7Cj4gKwkJY2Fz ZSBOQU5EX09QX0FERFJfSU5TVFI6Cj4gKwkJCWlmIChpbnN0ci0+Y3R4LmFkZHIubmFkZHJzID4g TFMxWF9OQU5EX01BWF9BRERSX0NZQykKPiArCQkJCXJldHVybiAtRU9QTk9UU1VQUDsKPiArCQkJ YnJlYWs7Cj4gKwkJZGVmYXVsdDoKPiArCQkJYnJlYWs7Cj4gKwkJfQo+ICsJfQo+ICsKPiArCWlm IChvcC0+bmluc3RycyA9PSA0ICYmCj4gKwkgICAgbHMxeF9uYW5kX2lzX2NtZF9zZXF1ZW5jZSgm b3AtPmluc3Ryc1swXSwgJm9wLT5pbnN0cnNbMl0pICYmCj4gKwkgICAgIWxzMXhfbmFuZF9pc19l cmFzZV9zZXF1ZW5jZSgmb3AtPmluc3Ryc1swXSwgJm9wLT5pbnN0cnNbMl0pKQo+ICsJCXJldHVy biAtRU9QTk9UU1VQUDsKPiArCj4gKwlpZiAob3AtPm5pbnN0cnMgPT0gNSkgewo+ICsJCWlmIChs czF4X25hbmRfaXNfY21kX3NlcXVlbmNlKCZvcC0+aW5zdHJzWzBdLCAmb3AtPmluc3Ryc1syXSkg JiYKPiArCQkgICAgIWxzMXhfbmFuZF9pc19yZWFkX3NlcXVlbmNlKCZvcC0+aW5zdHJzWzBdLCAm b3AtPmluc3Ryc1syXSkpCj4gKwkJCXJldHVybiAtRU9QTk9UU1VQUDsKPiArCj4gKwkJaWYgKGxz MXhfbmFuZF9pc19jbWRfc2VxdWVuY2UoJm9wLT5pbnN0cnNbMF0sICZvcC0+aW5zdHJzWzNdKSAm Jgo+ICsJCSAgICAhbHMxeF9uYW5kX2lzX3dyaXRlX3NlcXVlbmNlKCZvcC0+aW5zdHJzWzBdLCAm b3AtPmluc3Ryc1szXSkpCj4gKwkJCXJldHVybiAtRU9QTk9UU1VQUDsKPiArCX0KPiArCj4gKwly ZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIGludCBsczF4X25hbmRfZXhlY19vcChzdHJ1Y3Qg bmFuZF9jaGlwICpjaGlwLAo+ICsJCQkgICAgIGNvbnN0IHN0cnVjdCBuYW5kX29wZXJhdGlvbiAq b3AsCj4gKwkJCSAgICAgYm9vbCBjaGVja19vbmx5KQo+ICt7Cj4gKwlpZiAoY2hlY2tfb25seSkK PiArCQlyZXR1cm4gbHMxeF9uYW5kX2NoZWNrX29wKGNoaXAsIG9wKTsKPiArCgpJdCBsb29rc2Ug bGlrZSB5b3UncmUgcmUtZW5jb2RpbmcgYWxsIHlvdXIgcmVxdWlyZW1lbnRzIGluCmxzMXhfbmFu ZF9jaGVja19vcCgpLCB3aGVyZWFzIG5hbmRfb3BfcGFyc2VyX2V4ZWNfb3AoY2hlY2tfb25seSA6 PSB0cnVlKQpzaG91bGQgZ2l2ZSB5b3UgYWxyZWFkeSBhIGNlcnRhaW4gbnVtYmVyIG9mIHZlcmlm aWNhdGlvbnMgd2hpY2ggYXJlCnNraXBwZWQgaGVyZS4gSSdkIHN1Z2dlc3QgdG8gaW1wcm92ZSB0 aGlzIHRvIGF2b2lkIHJlcGV0aXRpb25zIGJldHdlZW4KdGhlIHR3by4gT2YgY291cnNlIHRoZSBz ZWNvbmQgcGFydCBvZiBuYW5kX2NoZWNrX29wIGlzIG5lY2Vzc2FyeSwgYnV0CnRoZSBpbml0aWFs IGNoZWNrcyBzZWVtIHJlZHVuZGFudCBhbmQgd291bGQgYmV0dGVyIGJlIHBlcmZvcm1lZCBieSB0 aGUgcGFyc2VyLgoKPiArCXJldHVybiBuYW5kX29wX3BhcnNlcl9leGVjX29wKGNoaXAsICZsczF4 X25hbmRfb3BfcGFyc2VyLCBvcCwgY2hlY2tfb25seSk7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQg bHMxeF9uYW5kX2F0dGFjaF9jaGlwKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXApCj4gK3sKCi4uLgoK PiArc3RhdGljIGludCBsczF4X25hbmRfY29udHJvbGxlcl9pbml0KHN0cnVjdCBsczF4X25hbmRf aG9zdCAqaG9zdCkKPiArewo+ICsJc3RydWN0IGRldmljZSAqZGV2ID0gaG9zdC0+ZGV2Owo+ICsJ c3RydWN0IGRtYV9jaGFuICpjaGFuOwo+ICsJc3RydWN0IGRtYV9zbGF2ZV9jb25maWcgY2ZnID0g e307Cj4gKwlpbnQgcmV0Owo+ICsKPiArCWhvc3QtPnJlZ21hcCA9IGRldm1fcmVnbWFwX2luaXRf bW1pbyhkZXYsIGhvc3QtPnJlZ19iYXNlLCAmbHMxeF9uYW5kX3JlZ21hcF9jb25maWcpOwo+ICsJ aWYgKElTX0VSUihob3N0LT5yZWdtYXApKQo+ICsJCXJldHVybiBkZXZfZXJyX3Byb2JlKGRldiwg UFRSX0VSUihob3N0LT5yZWdtYXApLCAiZmFpbGVkIHRvIGluaXQgcmVnbWFwXG4iKTsKPiArCj4g KwljaGFuID0gZG1hX3JlcXVlc3RfY2hhbihkZXYsICJyeHR4Iik7Cj4gKwlpZiAoSVNfRVJSKGNo YW4pKQo+ICsJCXJldHVybiBkZXZfZXJyX3Byb2JlKGRldiwgUFRSX0VSUihjaGFuKSwgImZhaWxl ZCB0byByZXF1ZXN0IERNQSBjaGFubmVsXG4iKTsKPiArCWhvc3QtPmRtYV9jaGFuID0gY2hhbjsK PiArCj4gKwljZmcuc3JjX2FkZHIgPSBob3N0LT5kbWFfYmFzZTsKPiArCWNmZy5zcmNfYWRkcl93 aWR0aCA9IERNQV9TTEFWRV9CVVNXSURUSF80X0JZVEVTOwo+ICsJY2ZnLmRzdF9hZGRyID0gaG9z dC0+ZG1hX2Jhc2U7CgpEb24ndCB5b3UgbmVlZCBhIGRtYV9hZGRyX3QgaGVyZSBpbnN0ZWFkPyBZ b3Ugc2hhbGwgcmVtYXAgdGhlIHJlc291cmNlLgoKPiArCWNmZy5kc3RfYWRkcl93aWR0aCA9IERN QV9TTEFWRV9CVVNXSURUSF80X0JZVEVTOwo+ICsJcmV0ID0gZG1hZW5naW5lX3NsYXZlX2NvbmZp Zyhob3N0LT5kbWFfY2hhbiwgJmNmZyk7Cj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiBkZXZfZXJy X3Byb2JlKGRldiwgcmV0LCAiZmFpbGVkIHRvIGNvbmZpZyBETUEgY2hhbm5lbFxuIik7Cj4gKwo+ ICsJaW5pdF9jb21wbGV0aW9uKCZob3N0LT5kbWFfY29tcGxldGUpOwo+ICsKPiArCWRldl9kYmco ZGV2LCAiZ290ICVzIGZvciAlcyBhY2Nlc3NcbiIsIGRtYV9jaGFuX25hbWUoaG9zdC0+ZG1hX2No YW4pLCBkZXZfbmFtZShkZXYpKTsKPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGlj IGludCBsczF4X25hbmRfY2hpcF9pbml0KHN0cnVjdCBsczF4X25hbmRfaG9zdCAqaG9zdCkKPiAr ewo+ICsJc3RydWN0IGRldmljZSAqZGV2ID0gaG9zdC0+ZGV2Owo+ICsJaW50IG5jaGlwcyA9IG9m X2dldF9jaGlsZF9jb3VudChkZXYtPm9mX25vZGUpOwo+ICsJc3RydWN0IGRldmljZV9ub2RlICpj aGlwX25wOwo+ICsJc3RydWN0IG5hbmRfY2hpcCAqY2hpcCA9ICZob3N0LT5jaGlwOwo+ICsJc3Ry dWN0IG10ZF9pbmZvICptdGQgPSBuYW5kX3RvX210ZChjaGlwKTsKPiArCWludCByZXQgPSAwOwo+ ICsKPiArCWlmIChuY2hpcHMgIT0gMSkKPiArCQlyZXR1cm4gZGV2X2Vycl9wcm9iZShkZXYsIC1F SU5WQUwsICJDdXJyZW50bHkgb25lIE5BTkQgY2hpcCBzdXBwb3J0ZWRcbiIpOwo+ICsKPiArCWNo aXBfbnAgPSBvZl9nZXRfbmV4dF9jaGlsZChkZXYtPm9mX25vZGUsIE5VTEwpOwo+ICsJaWYgKCFj aGlwX25wKQo+ICsJCXJldHVybiBkZXZfZXJyX3Byb2JlKGRldiwgLUVOT0RFViwgImZhaWxlZCB0 byBnZXQgY2hpbGQgbm9kZSBmb3IgTkFORCBjaGlwXG4iKTsKPiArCj4gKwljaGlwLT5jb250cm9s bGVyID0gJmhvc3QtPmNvbnRyb2xsZXI7Cj4gKwljaGlwLT5vcHRpb25zID0gTkFORF9OT19TVUJQ QUdFX1dSSVRFIHwgTkFORF9VU0VTX0RNQSB8IE5BTkRfQlJPS0VOX1hEOwo+ICsJY2hpcC0+YnVm X2FsaWduID0gMTY7Cj4gKwluYW5kX3NldF9jb250cm9sbGVyX2RhdGEoY2hpcCwgaG9zdCk7Cj4g KwluYW5kX3NldF9mbGFzaF9ub2RlKGNoaXAsIGNoaXBfbnApOwo+ICsKPiArCW10ZC0+ZGV2LnBh cmVudCA9IGRldjsKPiArCW10ZC0+bmFtZSA9ICJsczF4LW5hbmQiOwoKTm8sIHRoZSBuYW1lIGlz IGdvbm5hIGJlIGZpbGxlZCBhdXRvbWF0aWNhbGx5IHdoZW4geW91IGNhbGwKbmFuZF9zZXRfZmxh c2hfbm9kZSBJSVJDLgoKPiArCW10ZC0+b3duZXIgPSBUSElTX01PRFVMRTsKPiArCj4gKwlyZXQg PSBuYW5kX3NjYW4oY2hpcCwgMSk7Cj4gKwlpZiAocmV0KSB7Cj4gKwkJb2Zfbm9kZV9wdXQoY2hp cF9ucCk7Cj4gKwkJcmV0dXJuIHJldDsKPiArCX0KPiArCgpJdCBsb29rcyBsaWtlIHlvdXIgY29u dHJvbGxlciBkb2VzIG5vdCBzdXBwb3J0IGFueSBFQ0MgY29ycmVjdGlvbiwgaWYKdGhhdCdzIHRo ZSBjYXNlIHlvdSBtdXN0IG1ha2Ugc3VyZSBpdCdzIHByb3Blcmx5IGhhbmRsZWQgaW4gYXR0YWNo X2NoaXAKaG9vayBieSByZWZ1c2luZyB0byBwcm9iZSBpZiB0aGUgb25faG9zdCBlbmdpbmUgaXMg dXNlZC4KClRoYW5rcywKTWlxdcOobAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fCkxpbnV4IE1URCBkaXNjdXNzaW9uIG1haWxpbmcgbGlzdApo dHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LW10ZC8K From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20D291D63F0; Wed, 15 Jan 2025 18:54:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736967270; cv=none; b=POkXhtaU5mqqcwew4XD64MiO8oQvv3y6KlyfmPzalG8NMPlFJUcvbsnkfoMKo7XAieVT4CrKksWJjZr/T6pYgEvulLWvY8kBazUifpBK061+1vlRuIM+LUZFH5Czr0fR/WePB3FNdSs1vP99xxr3AzrY6VU+C5iFZrZw4zqcCqU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736967270; c=relaxed/simple; bh=UJgeODit0oPssfFa0cNX9lgrX4CDsdNt6vZPj6n+DkU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=ELNqK8NaAUWVZ+2ekKLKS5tbRsLTx/s3EXAlHIqdzT7OwKj6hbU9sYeXYA8Fsjo/PS7wDux0Z8Oz3g7ZMe/h42gjGpzl+pAKuz8Te3qZNLMwePRDaMbyh9TmMfoZ5BB4dytvnk/EYaf0VV3yaX+/ZGeNp8he1C3Frvd0M0M+G2E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=V/ngaiic; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="V/ngaiic" Received: by mail.gandi.net (Postfix) with ESMTPSA id B9F9D20004; Wed, 15 Jan 2025 18:54:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1736967265; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dQkA5beGm5rsGRni+AoHBlCFbxyYjwSxIyvpG2TQuog=; b=V/ngaiicgfFZCGHnAqnLEXmWdN0P32WNBk75Bx/XwZZ+DyMEP1pA6qGxXtkg324qsNXOF3 mPTpLSjYV/O0qRf4bodeTklG4P/QPw2RBG1ZnTjQfvo1o7JDqnX42RfS3XF1utjjELq04L FViT5xu7ttWp17foLc243O1EPVV2mmC+Ps9MNd7O+TKxyfO/LPbD/rwI/D8EnYa9D7TtTs piqh6avkFJyD9/EEssFKtOMUI/vrP1EWlCmPhCcGPH8fgOPcpDUe31ZtqTD/qhq2CxCFbV MY95jrYgJunQwQnFVBvGi+Xs8yHjrPdr4GMt2KwLQ+wra/KRrTo5k/cVYgVSgg== From: Miquel Raynal To: Keguang Zhang via B4 Relay Cc: Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , keguang.zhang@gmail.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Subject: Re: [PATCH v11 2/2] mtd: rawnand: Add Loongson-1 NAND Controller Driver In-Reply-To: <20241217-loongson1-nand-v11-2-b692c58988bb@gmail.com> (Keguang Zhang via's message of "Tue, 17 Dec 2024 18:16:50 +0800") References: <20241217-loongson1-nand-v11-0-b692c58988bb@gmail.com> <20241217-loongson1-nand-v11-2-b692c58988bb@gmail.com> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Wed, 15 Jan 2025 19:54:23 +0100 Message-ID: <87v7ufnc0w.fsf@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com Hello Keguang, On 17/12/2024 at 18:16:50 +08, Keguang Zhang via B4 Relay wrote: > +static int ls1x_nand_op_cmd_mapping(struct nand_chip *chip, struct ls1x_= nand_op *op, u8 opcode) > +{ > + struct ls1x_nand_host *host =3D nand_get_controller_data(chip); > + int ret =3D 0; This return code is unused. > + > + op->row_start =3D chip->page_shift + 1; > + > + /* The controller abstracts the following NAND operations. */ > + switch (opcode) { > + case NAND_CMD_STATUS: > + op->cmd_reg =3D LS1X_NAND_CMD_STATUS; > + break; > + case NAND_CMD_RESET: > + op->cmd_reg =3D LS1X_NAND_CMD_RESET; > + break; > + case NAND_CMD_READID: > + op->is_readid =3D true; > + op->cmd_reg =3D LS1X_NAND_CMD_READID; > + break; > + case NAND_CMD_ERASE1: > + op->is_erase =3D true; > + op->addrs_offset =3D 2; > + break; > + case NAND_CMD_ERASE2: > + if (!op->is_erase) > + return -EOPNOTSUPP; > + /* During erasing, row_start differs from the default value. */ ... > +static void ls1x_nand_trigger_op(struct ls1x_nand_host *host, struct ls1= x_nand_op *op) > +{ > + struct nand_chip *chip =3D &host->chip; > + struct mtd_info *mtd =3D nand_to_mtd(chip); > + int col0 =3D op->addrs[0]; > + short col; > + > + /* restore row address for column change */ > + if (op->is_change_column) { > + op->addr2_reg =3D readl(host->reg_base + LS1X_NAND_ADDR2); > + op->addr1_reg =3D readl(host->reg_base + LS1X_NAND_ADDR1); > + op->addr1_reg &=3D ~(mtd->writesize - 1); > + } This looks very suspicious. You should not have to do that and to be honest, I don't undertand what this means. > + > + if (!IS_ALIGNED(col0, chip->buf_align)) { > + col0 =3D ALIGN_DOWN(op->addrs[0], chip->buf_align); > + op->aligned_offset =3D op->addrs[0] - col0; > + op->addrs[0] =3D col0; > + } > + > + if (host->data->parse_address) > + host->data->parse_address(op); > + > + /* set address */ > + writel(op->addr1_reg, host->reg_base + LS1X_NAND_ADDR1); > + writel(op->addr2_reg, host->reg_base + LS1X_NAND_ADDR2); > + > + /* set operation length */ > + if (op->is_write || op->is_read || op->is_change_column) > + op->len =3D ALIGN(op->orig_len + op->aligned_offset, chip->buf_align); > + else if (op->is_erase) > + op->len =3D 1; > + else > + op->len =3D op->orig_len; > + > + writel(op->len, host->reg_base + LS1X_NAND_OP_NUM); > + > + /* set operation area */ > + col =3D op->addrs[1] << BITS_PER_BYTE | op->addrs[0]; > + if (op->orig_len && !op->is_readid) { > + if (col < mtd->writesize) > + op->cmd_reg |=3D LS1X_NAND_CMD_OP_MAIN; > + > + op->cmd_reg |=3D LS1X_NAND_CMD_OP_SPARE; > + } > + > + /* set operation scope */ > + if (host->data->op_scope_field) { > + unsigned int op_scope; > + > + switch (op->cmd_reg & LS1X_NAND_CMD_OP_AREA_MASK) { > + case LS1X_NAND_CMD_OP_MAIN: > + op_scope =3D mtd->writesize; > + break; > + case LS1X_NAND_CMD_OP_SPARE: > + op_scope =3D mtd->oobsize; > + break; > + case LS1X_NAND_CMD_OP_AREA_MASK: > + op_scope =3D mtd->writesize + mtd->oobsize; > + break; > + default: > + op_scope =3D 0; > + break; > + } Please get rid of this extra step. I'm not a big fan of it, but this can be very well simplified and this whole switch removed. > + > + op_scope <<=3D __ffs(host->data->op_scope_field); > + regmap_update_bits(host->regmap, LS1X_NAND_PARAM, > + host->data->op_scope_field, op_scope); > + } > + > + /* set command */ > + writel(op->cmd_reg, host->reg_base + LS1X_NAND_CMD); > + > + /* trigger operation */ > + regmap_write_bits(host->regmap, LS1X_NAND_CMD, LS1X_NAND_CMD_VALID, LS1= X_NAND_CMD_VALID); > +} > + ... > +static const struct nand_op_parser ls1x_nand_op_parser =3D NAND_OP_PARSE= R( > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_read_id_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, LS1X_NAND_MAX_ADDR_CYC), > + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_read_status_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_zerolen_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_zerolen_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, LS1X_NAND_MAX_ADDR_CYC), > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_data_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, LS1X_NAND_MAX_ADDR_CYC), > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), > + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_data_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, LS1X_NAND_MAX_ADDR_CYC), > + NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0), > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), > + ); > + > +static inline bool ls1x_nand_is_valid_cmd(u8 opcode) > +{ > + return opcode =3D=3D NAND_CMD_RESET || > + opcode =3D=3D NAND_CMD_READID || > + opcode =3D=3D NAND_CMD_ERASE1 || > + opcode =3D=3D NAND_CMD_ERASE2 || > + opcode =3D=3D NAND_CMD_STATUS || > + opcode =3D=3D NAND_CMD_SEQIN || > + opcode =3D=3D NAND_CMD_PAGEPROG || > + opcode =3D=3D NAND_CMD_RNDOUT || > + opcode =3D=3D NAND_CMD_RNDOUTSTART || > + opcode =3D=3D NAND_CMD_READ0 || > + opcode =3D=3D NAND_CMD_READSTART; > +} > + > +static inline bool ls1x_nand_is_cmd_sequence(const struct nand_op_instr = *instr1, > + const struct nand_op_instr *instr2) > +{ > + return instr1->type =3D=3D NAND_OP_CMD_INSTR && instr2->type =3D=3D NAN= D_OP_CMD_INSTR; > +} > + > +static inline bool ls1x_nand_is_erase_sequence(const struct nand_op_inst= r *instr1, > + const struct nand_op_instr *instr2) > +{ > + return instr1->ctx.cmd.opcode =3D=3D NAND_CMD_ERASE1 && > + instr2->ctx.cmd.opcode =3D=3D NAND_CMD_ERASE2; > +} > + > +static inline bool ls1x_nand_is_write_sequence(const struct nand_op_inst= r *instr1, > + const struct nand_op_instr *instr2) > +{ > + return instr1->ctx.cmd.opcode =3D=3D NAND_CMD_SEQIN && > + instr2->ctx.cmd.opcode =3D=3D NAND_CMD_PAGEPROG; > +} > + > +static inline bool ls1x_nand_is_read_sequence(const struct nand_op_instr= *instr1, > + const struct nand_op_instr *instr2) > +{ > + return (instr1->ctx.cmd.opcode =3D=3D NAND_CMD_READ0 && > + instr2->ctx.cmd.opcode =3D=3D NAND_CMD_READSTART) || > + (instr1->ctx.cmd.opcode =3D=3D NAND_CMD_RNDOUT && > + instr2->ctx.cmd.opcode =3D=3D NAND_CMD_RNDOUTSTART); > +} > + > +static int ls1x_nand_check_op(struct nand_chip *chip, const struct nand_= operation *op) > +{ > + const struct nand_op_instr *instr; > + int op_id; > + > + for (op_id =3D 0; op_id < op->ninstrs; op_id++) { > + instr =3D &op->instrs[op_id]; > + > + switch (instr->type) { > + case NAND_OP_CMD_INSTR: > + if (!ls1x_nand_is_valid_cmd(instr->ctx.cmd.opcode)) > + return -EOPNOTSUPP; > + break; > + case NAND_OP_ADDR_INSTR: > + if (instr->ctx.addr.naddrs > LS1X_NAND_MAX_ADDR_CYC) > + return -EOPNOTSUPP; > + break; > + default: > + break; > + } > + } > + > + if (op->ninstrs =3D=3D 4 && > + ls1x_nand_is_cmd_sequence(&op->instrs[0], &op->instrs[2]) && > + !ls1x_nand_is_erase_sequence(&op->instrs[0], &op->instrs[2])) > + return -EOPNOTSUPP; > + > + if (op->ninstrs =3D=3D 5) { > + if (ls1x_nand_is_cmd_sequence(&op->instrs[0], &op->instrs[2]) && > + !ls1x_nand_is_read_sequence(&op->instrs[0], &op->instrs[2])) > + return -EOPNOTSUPP; > + > + if (ls1x_nand_is_cmd_sequence(&op->instrs[0], &op->instrs[3]) && > + !ls1x_nand_is_write_sequence(&op->instrs[0], &op->instrs[3])) > + return -EOPNOTSUPP; > + } > + > + return 0; > +} > + > +static int ls1x_nand_exec_op(struct nand_chip *chip, > + const struct nand_operation *op, > + bool check_only) > +{ > + if (check_only) > + return ls1x_nand_check_op(chip, op); > + It lookse like you're re-encoding all your requirements in ls1x_nand_check_op(), whereas nand_op_parser_exec_op(check_only :=3D true) should give you already a certain number of verifications which are skipped here. I'd suggest to improve this to avoid repetitions between the two. Of course the second part of nand_check_op is necessary, but the initial checks seem redundant and would better be performed by the pars= er. > + return nand_op_parser_exec_op(chip, &ls1x_nand_op_parser, op, check_onl= y); > +} > + > +static int ls1x_nand_attach_chip(struct nand_chip *chip) > +{ ... > +static int ls1x_nand_controller_init(struct ls1x_nand_host *host) > +{ > + struct device *dev =3D host->dev; > + struct dma_chan *chan; > + struct dma_slave_config cfg =3D {}; > + int ret; > + > + host->regmap =3D devm_regmap_init_mmio(dev, host->reg_base, &ls1x_nand_= regmap_config); > + if (IS_ERR(host->regmap)) > + return dev_err_probe(dev, PTR_ERR(host->regmap), "failed to init regma= p\n"); > + > + chan =3D dma_request_chan(dev, "rxtx"); > + if (IS_ERR(chan)) > + return dev_err_probe(dev, PTR_ERR(chan), "failed to request DMA channe= l\n"); > + host->dma_chan =3D chan; > + > + cfg.src_addr =3D host->dma_base; > + cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; > + cfg.dst_addr =3D host->dma_base; Don't you need a dma_addr_t here instead? You shall remap the resource. > + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; > + ret =3D dmaengine_slave_config(host->dma_chan, &cfg); > + if (ret) > + return dev_err_probe(dev, ret, "failed to config DMA channel\n"); > + > + init_completion(&host->dma_complete); > + > + dev_dbg(dev, "got %s for %s access\n", dma_chan_name(host->dma_chan), d= ev_name(dev)); > + > + return 0; > +} > + > +static int ls1x_nand_chip_init(struct ls1x_nand_host *host) > +{ > + struct device *dev =3D host->dev; > + int nchips =3D of_get_child_count(dev->of_node); > + struct device_node *chip_np; > + struct nand_chip *chip =3D &host->chip; > + struct mtd_info *mtd =3D nand_to_mtd(chip); > + int ret =3D 0; > + > + if (nchips !=3D 1) > + return dev_err_probe(dev, -EINVAL, "Currently one NAND chip supported\= n"); > + > + chip_np =3D of_get_next_child(dev->of_node, NULL); > + if (!chip_np) > + return dev_err_probe(dev, -ENODEV, "failed to get child node for NAND = chip\n"); > + > + chip->controller =3D &host->controller; > + chip->options =3D NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA | NAND_BROKEN_X= D; > + chip->buf_align =3D 16; > + nand_set_controller_data(chip, host); > + nand_set_flash_node(chip, chip_np); > + > + mtd->dev.parent =3D dev; > + mtd->name =3D "ls1x-nand"; No, the name is gonna be filled automatically when you call nand_set_flash_node IIRC. > + mtd->owner =3D THIS_MODULE; > + > + ret =3D nand_scan(chip, 1); > + if (ret) { > + of_node_put(chip_np); > + return ret; > + } > + It looks like your controller does not support any ECC correction, if that's the case you must make sure it's properly handled in attach_chip hook by refusing to probe if the on_host engine is used. Thanks, Miqu=C3=A8l