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From: Jani Nikula <jani.nikula@linux.intel.com>
To: David Kershner <david.kershner@intel.com>,
	david.kershner@intel.com, intel-xe@lists.freedesktop.org,
	michael.j.ruhl@intel.com, john.fleck@intel.com,
	lucas.demarchi@intel.com, rodrigo.vivi@intel.com,
	matthew.d.roper@intel.com
Subject: Re: [PATCH v3 1/3] drm/xe: Introduce XeLink device
Date: Fri, 15 Dec 2023 17:06:44 +0200	[thread overview]
Message-ID: <87v88zv723.fsf@intel.com> (raw)
In-Reply-To: <20231213214525.2584729-2-david.kershner@intel.com>

On Wed, 13 Dec 2023, David Kershner <david.kershner@intel.com> wrote:
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index d1a48456e9a3..6b3ff57f358c 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -21,6 +21,7 @@
>  #include "xe_pmu.h"
>  #include "xe_sriov_types.h"
>  #include "xe_step_types.h"
> +#include "xe_link.h"

Nothing in this file requires you to include xe_link.h.

I've put a lot of effort into untangling the insane header
interdependencies in i915; please take care to not create the same in
xe.

BR,
Jani.

>  
>  #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>  #include "soc/intel_pch.h"
> @@ -255,6 +256,8 @@ struct xe_device {
>  		u8 has_asid:1;
>  		/** @force_execlist: Forced execlist submission */
>  		u8 force_execlist:1;
> +		/** @has_xelink: Has XeLink */
> +		u8 has_xelink:1;
>  		/** @has_flat_ccs: Whether flat CCS metadata is used */
>  		u8 has_flat_ccs:1;
>  		/** @has_llc: Device has a shared CPU+GPU last level cache */
> @@ -439,6 +442,28 @@ struct xe_device {
>  	/** @needs_flr_on_fini: requests function-reset on fini */
>  	bool needs_flr_on_fini;
>  
> +	/** @xelink: XeLink information, for those gpus with XeLink connectivity */
> +	struct {
> +		/** @ops: shared interface operations */
> +		const struct xelink_ops *ops;
> +		/** @handle: XeLink device handle */
> +		void *handle;
> +		/** @pd: platform data needed for auxiliary bus */
> +		struct xelink_pdata *pd;
> +		/** @dpa: base device physical address */
> +		u64 dpa;
> +		/** @irq_base: base IRQ for multi tile devices */
> +		int irq_base;
> +		/** @index: internal index for xe devices */
> +		int index;
> +		/** @xelink_id: XeLink id generated by the XeLink device */
> +		u32 xelink_id;
> +		/** @socket_id: socket from certain platforms */
> +		u8 socket_id;
> +		/* @present: Reflect PUNIT presence information */
> +		bool present;
> +	} xelink;
> +
>  	/* private: */
>  
>  #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index f74684660475..1e8c0d3cf17f 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -358,6 +358,8 @@ struct xe_gt {
>  		/** @oob: bitmap with active OOB workaroudns */
>  		unsigned long *oob;
>  	} wa_active;
> +	/** @xelink_irq: IRQ value assigned to the Xelink device */
> +	int xelink_irq;
>  };
>  
>  #endif

-- 
Jani Nikula, Intel

  reply	other threads:[~2023-12-15 15:06 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-13 21:45 [PATCH v3 0/3] Add support for XeLink device David Kershner
2023-12-13 21:45 ` [PATCH v3 1/3] drm/xe: Introduce " David Kershner
2023-12-15 15:06   ` Jani Nikula [this message]
2023-12-13 21:45 ` [PATCH v3 2/3] drm/xe: Teach Xe how to use objects with XeLink connectivity David Kershner
2023-12-13 21:45 ` [PATCH v3 3/3] drm/xe/uapi: Augment query ioctl to allow for fabric David Kershner
2023-12-13 21:48 ` ✓ CI.Patch_applied: success for Add support for XeLink device (rev5) Patchwork
2023-12-13 21:48 ` ✗ CI.checkpatch: warning " Patchwork
2023-12-13 21:49 ` ✓ CI.KUnit: success " Patchwork
2023-12-13 21:56 ` ✓ CI.Build: " Patchwork
2023-12-13 21:57 ` ✓ CI.Hooks: " Patchwork
2023-12-13 21:58 ` ✓ CI.checksparse: " Patchwork
2023-12-13 22:32 ` ✓ CI.BAT: " Patchwork
2023-12-15 14:50 ` [PATCH v3 0/3] Add support for XeLink device Ruhl, Michael J
2023-12-15 16:37   ` Lucas De Marchi
2023-12-15 16:54     ` Kershner, David

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