From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA92AEB64DD for ; Mon, 14 Aug 2023 02:08:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231786AbjHNCHy (ORCPT ); Sun, 13 Aug 2023 22:07:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230501AbjHNCHo (ORCPT ); Sun, 13 Aug 2023 22:07:44 -0400 Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D00C5E54 for ; Sun, 13 Aug 2023 19:07:41 -0700 (PDT) References: User-agent: mu4e 1.10.6; emacs 30.0.50 From: Sam James To: Helge Deller Cc: Sam James , linux-parisc@vger.kernel.org Subject: Re: [PATCH v2] Fix CONFIG_TLB_PTLOCK to work with lightweight spinlock checks Date: Mon, 14 Aug 2023 03:06:40 +0100 Organization: Gentoo In-reply-to: Message-ID: <87v8di5qc6.fsf@gentoo.org> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org Helge Deller writes: > For the TLB_PTLOCK checks we used an optimization to store the spc > register into the spinlock to unlock it. This optimization works as > long as the lightweight spinlock checks (CONFIG_LIGHTWEIGHT_SPINLOCK_CHECK) > aren't enabled, because they really check if the lock word is zero or > __ARCH_SPIN_LOCK_UNLOCKED_VAL and abort with a kernel crash > ("Spinlock was trashed") otherwise. > > Drop that optimization to make it possible to activate both checks > at the same time. > > Noticed-by: Sam James > Signed-off-by: Helge Deller > Cc: stable@vger.kernel.org # v6.4+ > Fixes: 15e64ef6520e ("parisc: Add lightweight spinlock checks") Thanks! Works. Tested-by: Sam James > > --- > v2: > - missed to fix another unlock in previous patch > - resend, because my mail provider decided to scramble my outgoing > mails and drop tabs, so that the patches don't apply cleanly > any longer. > > --- > > > diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S > index 0e5ebfe8d9d2..8cd88a1bf588 100644 > --- a/arch/parisc/kernel/entry.S > +++ b/arch/parisc/kernel/entry.S > @@ -25,6 +25,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -406,7 +407,7 @@ > LDREG 0(\ptp),\pte > bb,<,n \pte,_PAGE_PRESENT_BIT,3f > b \fault > - stw \spc,0(\tmp) > + stw \tmp1,0(\tmp) /* restore lock value */ > 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) > #endif > 2: LDREG 0(\ptp),\pte > @@ -415,24 +416,22 @@ > .endm > > /* Release page_table_lock without reloading lock address. > - Note that the values in the register spc are limited to > - NR_SPACE_IDS (262144). Thus, the stw instruction always > - stores a nonzero value even when register spc is 64 bits. > We use an ordered store to ensure all prior accesses are > performed prior to releasing the lock. */ > - .macro ptl_unlock0 spc,tmp > + .macro ptl_unlock0 spc,tmp,tmp2 > #ifdef CONFIG_TLB_PTLOCK > -98: or,COND(=) %r0,\spc,%r0 > - stw,ma \spc,0(\tmp) > +98: ldi __ARCH_SPIN_LOCK_UNLOCKED_VAL, \tmp2 > + or,COND(=) %r0,\spc,%r0 > + stw,ma \tmp2,0(\tmp) > 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) > #endif > .endm > > /* Release page_table_lock. */ > - .macro ptl_unlock1 spc,tmp > + .macro ptl_unlock1 spc,tmp,tmp2 > #ifdef CONFIG_TLB_PTLOCK > 98: get_ptl \tmp > - ptl_unlock0 \spc,\tmp > + ptl_unlock0 \spc,\tmp,\tmp2 > 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) > #endif > .endm > @@ -1125,7 +1124,7 @@ dtlb_miss_20w: > > idtlbt pte,prot > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1151,7 +1150,7 @@ nadtlb_miss_20w: > > idtlbt pte,prot > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1185,7 +1184,7 @@ dtlb_miss_11: > > mtsp t1, %sr1 /* Restore sr1 */ > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1218,7 +1217,7 @@ nadtlb_miss_11: > > mtsp t1, %sr1 /* Restore sr1 */ > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1247,7 +1246,7 @@ dtlb_miss_20: > > idtlbt pte,prot > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1275,7 +1274,7 @@ nadtlb_miss_20: > > idtlbt pte,prot > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1320,7 +1319,7 @@ itlb_miss_20w: > > iitlbt pte,prot > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1344,7 +1343,7 @@ naitlb_miss_20w: > > iitlbt pte,prot > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1378,7 +1377,7 @@ itlb_miss_11: > > mtsp t1, %sr1 /* Restore sr1 */ > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1402,7 +1401,7 @@ naitlb_miss_11: > > mtsp t1, %sr1 /* Restore sr1 */ > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1432,7 +1431,7 @@ itlb_miss_20: > > iitlbt pte,prot > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1452,7 +1451,7 @@ naitlb_miss_20: > > iitlbt pte,prot > > - ptl_unlock1 spc,t0 > + ptl_unlock1 spc,t0,t1 > rfir > nop > > @@ -1482,7 +1481,7 @@ dbit_trap_20w: > > idtlbt pte,prot > > - ptl_unlock0 spc,t0 > + ptl_unlock0 spc,t0,t1 > rfir > nop > #else > @@ -1508,7 +1507,7 @@ dbit_trap_11: > > mtsp t1, %sr1 /* Restore sr1 */ > > - ptl_unlock0 spc,t0 > + ptl_unlock0 spc,t0,t1 > rfir > nop > > @@ -1528,7 +1527,7 @@ dbit_trap_20: > > idtlbt pte,prot > > - ptl_unlock0 spc,t0 > + ptl_unlock0 spc,t0,t1 > rfir > nop > #endif