Re: [Intel-gfx] [PATCH] drm/i915/dsc: Source supports DSC from DISPLAY_VER >= 11

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 02 Nov 2022, Swati Sharma <swati2.sharma@intel.com> wrote:
> Hi Matt,
>
> Yes. Though h/w supports DSC from gen10, DSC is enabled from gen11+ from 
> driver.
> We can see "has_dsc" flag enabled in gen11+.
> #define GEN11_FEATURES \
>  >-------.__runtime.has_dsc = 1, \
>
> Also, in the driver intel_dsc_source_support(), it is
> if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A)
>                  return true;
> So, we should align DISPLAY_VER check according to DSC enablement
> from driver.

The real fix would be to use intel_dsc_source_support() as the single
point of truth instead of sprinkled all over the place. Especially since
that also takes fusing into account.

BR,
Jani.



>
> On 02-Nov-22 2:50 AM, Matt Roper wrote:
>> On Tue, Nov 01, 2022 at 01:29:27PM +0530, Swati Sharma wrote:
>>> i915 driver supports DSC from DISPLAY_VER >= 11. Fix it.
>> 
>> Bspec 19713 indicates that GLK (i.e., our only display version 10
>> platform) does support DSC.  Are you saying that there's other GLK
>> enablement missing in the driver right now that prevents DSC from
>> working?
>> 
>> 
>> Matt
>> 
>>>
>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 7400d6b4c587..02e64f0284d8 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -1012,7 +1012,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>>>   	 * Output bpp is stored in 6.4 format so right shift by 4 to get the
>>>   	 * integer value since we support only integer values of bpp.
>>>   	 */
>>> -	if (DISPLAY_VER(dev_priv) >= 10 &&
>>> +	if (DISPLAY_VER(dev_priv) >= 11 &&
>>>   	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
>>>   		/*
>>>   		 * TBD pass the connector BPC,
>>> @@ -2906,7 +2906,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>>>   	intel_dp_set_max_sink_lane_count(intel_dp);
>>>   
>>>   	/* Read the eDP DSC DPCD registers */
>>> -	if (DISPLAY_VER(dev_priv) >= 10)
>>> +	if (DISPLAY_VER(dev_priv) >= 11)
>>>   		intel_dp_get_dsc_sink_cap(intel_dp);
>>>   
>>>   	/*
>>> -- 
>>> 2.25.1
>>>
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center