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[139.178.84.217]) by mx.google.com with ESMTPS id t3si14106406oth.234.2021.11.29.01.19.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 29 Nov 2021 01:19:44 -0800 (PST) Received-SPF: pass (google.com: domain of maz@kernel.org designates 139.178.84.217 as permitted sender) client-ip=139.178.84.217; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=H2NDpVnb; spf=pass (google.com: domain of maz@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=maz@kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 83F43611F9; Mon, 29 Nov 2021 09:19:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EAB61C004E1; Mon, 29 Nov 2021 09:19:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638177583; bh=Nt1W7Smat1fUpYIQt6EYKDfPMsXrSZ/yrbGkUkAu7EY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=H2NDpVnbfnplod5AzC9w0pq0PUmV3pU5rxGrqmBLJPopJcZEg8gu5fbX6yY8DR4NM yFuDdtjMwY5NoU3q6/4ESHkiAw7tdtc5o1DDN9PsBRUNS7UV+r76qXNVt4JJo7AfTD WhOmTd7TBUDe/PO5GYR9lhoVBr8093Qj532QMb6OIvUH2H+fy2FvbBPGP6vzzEF/4k hbwSa2ei+cIKY/xhx+JpT43X0FR6+fl8qruqxUiZ9S1wt1xmWWndD9k3i/Q9EhNFOU Rr3j/UcSm4LtIQ1ewQ0LvxBykClK8l6ItlF4K4H1gc2wr5rM/xuOx1SDoMtwAXomzS LovjdA6Wv10gg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mrcp2-008Yv8-IS; Mon, 29 Nov 2021 09:19:40 +0000 Date: Mon, 29 Nov 2021 09:19:33 +0000 Message-ID: <87v90bmi8q.wl-maz@kernel.org> From: Marc Zyngier To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Alex =?UTF-8?B?QmVubsOp?= =?UTF-8?B?ZQ==?= , Richard Henderson , Shashi Mallela Subject: Re: [PATCH for-6.2? 0/2] arm_gicv3: Fix handling of LPIs in list registers In-Reply-To: <20211126163915.1048353-1-peter.maydell@linaro.org> References: <20211126163915.1048353-1-peter.maydell@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.bennee@linaro.org, richard.henderson@linaro.org, shashi.mallela@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-TUID: DbXyKsXMGByR Hi Peter, On Fri, 26 Nov 2021 16:39:13 +0000, Peter Maydell wrote: > > (Marc: cc'd you on this one in case you're still using QEMU > to test KVM stuff with, in which case you might have run into > the bug this is fixing.) Amusingly enough, I have recently fixed [1] a very similar issue with the ICV_*_EL1 emulation that KVM uses when dealing with sub-par HW (ThunderX and M1). When writing this a very long while ago, I modelled it so that LPIs wouldn't have an Active state, similar to bare metal. As it turns out, the pseudocode actually treats LPIs almost like any other interrupt, and is quite happy to carry an active bit that eventually gets exposed to the hypervisor. I don't think this ever caused any issue, but I'd be pretty happy to see the QEMU implementation fixed. For the whole series: Reviewed-by: Marc Zyngier Thanks, M. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm64/kvm/hyp/vgic-v3-sr.c?id=9d449c71bd8f74282e84213c8f0b8328293ab0a7 -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30B92C433F5 for ; Mon, 29 Nov 2021 09:21:07 +0000 (UTC) Received: from localhost ([::1]:57752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mrcqP-0005Tm-Rd for qemu-devel@archiver.kernel.org; Mon, 29 Nov 2021 04:21:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mrcpH-000429-D2; Mon, 29 Nov 2021 04:19:57 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:44108) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mrcpF-0000He-6O; Mon, 29 Nov 2021 04:19:55 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 83F43611F9; Mon, 29 Nov 2021 09:19:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EAB61C004E1; Mon, 29 Nov 2021 09:19:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638177583; bh=Nt1W7Smat1fUpYIQt6EYKDfPMsXrSZ/yrbGkUkAu7EY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=H2NDpVnbfnplod5AzC9w0pq0PUmV3pU5rxGrqmBLJPopJcZEg8gu5fbX6yY8DR4NM yFuDdtjMwY5NoU3q6/4ESHkiAw7tdtc5o1DDN9PsBRUNS7UV+r76qXNVt4JJo7AfTD WhOmTd7TBUDe/PO5GYR9lhoVBr8093Qj532QMb6OIvUH2H+fy2FvbBPGP6vzzEF/4k hbwSa2ei+cIKY/xhx+JpT43X0FR6+fl8qruqxUiZ9S1wt1xmWWndD9k3i/Q9EhNFOU Rr3j/UcSm4LtIQ1ewQ0LvxBykClK8l6ItlF4K4H1gc2wr5rM/xuOx1SDoMtwAXomzS LovjdA6Wv10gg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mrcp2-008Yv8-IS; Mon, 29 Nov 2021 09:19:40 +0000 Date: Mon, 29 Nov 2021 09:19:33 +0000 Message-ID: <87v90bmi8q.wl-maz@kernel.org> From: Marc Zyngier To: Peter Maydell Subject: Re: [PATCH for-6.2? 0/2] arm_gicv3: Fix handling of LPIs in list registers In-Reply-To: <20211126163915.1048353-1-peter.maydell@linaro.org> References: <20211126163915.1048353-1-peter.maydell@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, alex.bennee@linaro.org, richard.henderson@linaro.org, shashi.mallela@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Received-SPF: pass client-ip=139.178.84.217; envelope-from=maz@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.717, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Shashi Mallela , qemu-arm@nongnu.org, Alex =?UTF-8?B?QmVubsOp?= =?UTF-8?B?ZQ==?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Peter, On Fri, 26 Nov 2021 16:39:13 +0000, Peter Maydell wrote: > > (Marc: cc'd you on this one in case you're still using QEMU > to test KVM stuff with, in which case you might have run into > the bug this is fixing.) Amusingly enough, I have recently fixed [1] a very similar issue with the ICV_*_EL1 emulation that KVM uses when dealing with sub-par HW (ThunderX and M1). When writing this a very long while ago, I modelled it so that LPIs wouldn't have an Active state, similar to bare metal. As it turns out, the pseudocode actually treats LPIs almost like any other interrupt, and is quite happy to carry an active bit that eventually gets exposed to the hypervisor. I don't think this ever caused any issue, but I'd be pretty happy to see the QEMU implementation fixed. For the whole series: Reviewed-by: Marc Zyngier Thanks, M. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm64/kvm/hyp/vgic-v3-sr.c?id=9d449c71bd8f74282e84213c8f0b8328293ab0a7 -- Without deviation from the norm, progress is not possible.