From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Navare\, Manasi" <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 02/11] drm/i915/display/vrr: Create VRR file and add VRR capability check
Date: Thu, 03 Dec 2020 18:35:29 +0200 [thread overview]
Message-ID: <87v9dic0fi.fsf@intel.com> (raw)
In-Reply-To: <20201202224030.GB26911@labuser-Z97X-UD5H>
On Wed, 02 Dec 2020, "Navare, Manasi" <manasi.d.navare@intel.com> wrote:
> On Tue, Dec 01, 2020 at 02:21:56PM -0800, Navare, Manasi wrote:
>> On Tue, Nov 10, 2020 at 12:39:08PM +0200, Jani Nikula wrote:
>> > > +{
>> > > + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
>> >
>> > I kind of feel like either the function should a) ensure it's okay to do
>> > intel_attached_dp() and return false if not, or b) just use struct
>> > intel_dp as the parameter.
>> >
>> > As it is, passing a non-dp connector to this function will fail either
>> > subtly or spectacularly, but not graciously.
>
> Actually after doing some code rewriting, I think it is best to still pass
> the drm connector but I am adding the check now for connector type
> Only if its eDP or DP now I get the intel_dp.
> Future we can add HDMI there as well.
It's fine, as long as we don't cast to intel_dp unless we know it's
intel_dp.
>> > > +
>> > > + /*
>> > > + * DP Sink is capable of Variable refresh video timings if
>> > > + * Ignore MSA bit is set in DPCD.
>> > > + * EDID monitor range also should be atleast 10 for reasonable
>> > > + * Adaptive sync/ VRR end user experience.
>> > > + */
>> >
>> > Please fix typos etc.
>>
>> Did I miss some typos, I dont see any in the above comment?
Odd capitalization, "atleast", "sync/ VRR", maybe also reflow the
paragraph.
I know it's nitpicking, but other people will read the comment many,
many more times than you write it. ;)
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2020-12-03 16:35 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-22 22:26 [Intel-gfx] [PATCH 00/11] VRR/Adaptive Sync enabling in i915 Manasi Navare
2020-10-22 22:26 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add REG_FIELD_PREP to VRR register def Manasi Navare
2020-11-10 10:13 ` Jani Nikula
2020-12-01 22:41 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 02/11] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2020-11-10 10:39 ` Jani Nikula
2020-12-01 22:21 ` Navare, Manasi
2020-12-02 22:40 ` Navare, Manasi
2020-12-03 16:35 ` Jani Nikula [this message]
2020-12-03 19:38 ` Navare, Manasi
2020-11-10 16:06 ` Ville Syrjälä
2020-11-10 18:48 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 03/11] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2020-11-10 10:41 ` Jani Nikula
2020-12-01 22:46 ` Navare, Manasi
2020-12-03 16:37 ` Jani Nikula
2020-12-03 19:37 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 04/11] drm/i915/display/dp: Add VRR crtc state variables Manasi Navare
2020-11-10 10:41 ` Jani Nikula
2020-12-01 22:49 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 05/11] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2020-11-10 10:47 ` Jani Nikula
2020-12-01 22:52 ` Navare, Manasi
2020-12-02 22:38 ` Navare, Manasi
2020-12-03 16:39 ` Jani Nikula
2020-12-03 19:36 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 06/11] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2020-10-22 22:27 ` [Intel-gfx] [PATCH 07/11] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2020-11-10 10:56 ` Jani Nikula
2020-12-01 22:56 ` Navare, Manasi
2020-12-03 16:40 ` Jani Nikula
2020-10-22 22:27 ` [Intel-gfx] [PATCH 08/11] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2020-11-10 10:59 ` Jani Nikula
2020-12-01 22:57 ` Navare, Manasi
2020-12-03 19:58 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 09/11] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2020-11-10 11:01 ` Jani Nikula
2020-12-01 22:34 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 10/11] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2020-12-01 22:59 ` Navare, Manasi
2020-12-03 16:49 ` Jani Nikula
2020-12-03 19:33 ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 11/11] drm/i915/display: Add HW state readout for VRR Manasi Navare
2020-10-23 17:42 ` [Intel-gfx] [PATCH v2 " Manasi Navare
2020-10-22 22:37 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for VRR/Adaptive Sync enabling in i915 Patchwork
2020-10-23 17:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync enabling in i915 (rev2) Patchwork
2020-10-23 17:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-23 18:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-23 21:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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