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From: Jani Nikula <jani.nikula@intel.com>
To: "Kulkarni, Vandita" <vandita.kulkarni@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "Syrjala, Ville" <ville.syrjala@intel.com>
Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format
Date: Tue, 30 Apr 2019 15:46:00 +0300	[thread overview]
Message-ID: <87v9yvpson.fsf@intel.com> (raw)
In-Reply-To: <57510F3E2013164E925CD03ED7512A3B7FEEE20A@BGSMSX110.gar.corp.intel.com>

On Tue, 30 Apr 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Tuesday, April 30, 2019 3:03 PM
>> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Syrjala, Ville <ville.syrjala@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format
>> 
>> On Tue, 30 Apr 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
>> > Read back the pixel fomrat register and get the bpp.
>> >
>> > v2: Read the PIPE_MISC register (Jani).
>> >
>> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/icl_dsi.c   | 3 +++
>> >  drivers/gpu/drm/i915/intel_dsi.h | 1 +
>> >  drivers/gpu/drm/i915/vlv_dsi.c   | 2 +-
>> >  3 files changed, 5 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> > b/drivers/gpu/drm/i915/icl_dsi.c index dbb2712..5cc58b2 100644
>> > --- a/drivers/gpu/drm/i915/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> > @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct
>> > intel_encoder *encoder,  {
>> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> >  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> > +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
>> >
>> >  	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
>> >  	pipe_config->port_clock =
>> > @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct
>> intel_encoder *encoder,
>> >  	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
>> >  	gen11_dsi_get_timings(encoder, pipe_config);
>> >  	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
>> > +	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
>> >  }
>> >
>> >  static int gen11_dsi_compute_config(struct intel_encoder *encoder, @@
>> > -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,
>> >  	struct drm_display_mode *adjusted_mode =
>> >  					&pipe_config->base.adjusted_mode;
>> >
>> > +	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> >  	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
>> >  	intel_pch_panel_fitting(crtc, pipe_config,
>> > conn_state->scaling_mode);
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi.h
>> > b/drivers/gpu/drm/i915/intel_dsi.h
>> > index 705a609..cb9e3b9 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi.h
>> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> > @@ -166,6 +166,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct
>> > drm_connector *connector,  struct intel_dsi_host *intel_dsi_host_init(struct
>> intel_dsi *intel_dsi,
>> >  					   const struct mipi_dsi_host_ops
>> *funcs,
>> >  					   enum port port);
>> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
>> 
>> Until now this was internal to vlv_dsi.c and it was fine. Now, I think I'd move this
>> to intel_display.c alongside haswell_set_pipemisc.
> Ok, so I ll move thjs to intel_display.c and call it from haswell_get_pipe_config for is_dsi and gen >= 9

I'd actually prefer to call it from dsi encoder code instead.

BR,
Jani.

> Thanks,
> Vandita
>> 
>> Ville already has patches to rename haswell_set_pipemisc to bdw_set_pipemisc.
>> 
>> BR,
>> Jani.
>> 
>> 
>> >
>> >  /* vlv_dsi_pll.c */
>> >  int vlv_dsi_pll_compute(struct intel_encoder *encoder, diff --git
>> > a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
>> > index b4c6583..790ada8 100644
>> > --- a/drivers/gpu/drm/i915/vlv_dsi.c
>> > +++ b/drivers/gpu/drm/i915/vlv_dsi.c
>> > @@ -260,7 +260,7 @@ static void band_gap_reset(struct drm_i915_private
>> *dev_priv)
>> >  	vlv_flisdsi_put(dev_priv);
>> >  }
>> >
>> > -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>> >  {
>> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >  	u32 tmp;
>> 
>> --
>> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-04-30 12:43 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-30  8:17 [v2 1/3] drm/i915: Fix the pipe state timing mismatch warnings Vandita Kulkarni
2019-04-30  8:17 ` [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni
2019-04-30  9:33   ` Jani Nikula
2019-04-30 12:39     ` Kulkarni, Vandita
2019-04-30 12:46       ` Jani Nikula [this message]
2019-04-30 12:59         ` Kulkarni, Vandita
2019-04-30  8:17 ` [v2 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch Vandita Kulkarni
2019-04-30 13:04 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings Patchwork

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