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References: <20180119045438.28582-1-richard.henderson@linaro.org>
	<20180119045438.28582-10-richard.henderson@linaro.org>
From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <20180119045438.28582-10-richard.henderson@linaro.org>
Date: Mon, 22 Jan 2018 12:04:21 +0000
Message-ID: <87vafuje0q.fsf@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH v2 09/16] target/arm: Add predicate
 registers for SVE
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To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org


Richard Henderson <richard.henderson@linaro.org> writes:

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 57d805b5d8..132da359b5 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -186,6 +186,15 @@ typedef struct ARMVectorReg {
>      uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
>  } ARMVectorReg;
>
> +/* In AArch32 mode, predicate registers do not exist at all.  */
> +typedef struct ARMPredicateReg {
> +#ifdef TARGET_AARCH64
> +    uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
> +#else
> +    uint64_t p[0];
> +#endif
> +} ARMPredicateReg;
> +
>
>  typedef struct CPUARMState {
>      /* Regs for current mode.  */
> @@ -513,6 +522,9 @@ typedef struct CPUARMState {
>      struct {
>          ARMVectorReg zregs[32];
>
> +        /* Store FFR as pregs[16] to make it easier to treat as any othe=
r.  */
> +        ARMPredicateReg pregs[17];
> +

What happens if code tries to accidentally access this on the 32 bit build?

>          uint32_t xregs[16];
>          /* We store these fpcsr fields separately for convenience.  */
>          int vec_len;


--
Alex Benn=C3=A9e