From mboxrd@z Thu Jan 1 00:00:00 1970 From: eric@anholt.net (Eric Anholt) Date: Thu, 17 Aug 2017 09:12:36 -0700 Subject: [GIT PULL 2/2] bcm2835-soc-next-2017-08-15 In-Reply-To: <36766926-c8d6-b768-59b6-4ff302a6a5ba@gmail.com> References: <20170815180325.12809-1-eric@anholt.net> <20170815180325.12809-2-eric@anholt.net> <36766926-c8d6-b768-59b6-4ff302a6a5ba@gmail.com> Message-ID: <87valmgoln.fsf@eliezer.anholt.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Florian Fainelli writes: > On 08/15/2017 11:03 AM, Eric Anholt wrote: >> The following changes since commit f29c256853b7412961d3ee80ca525bd2530573db: >> >> ARM: dts: bcm283x: Add 32-bit enable method for SMP (2017-08-14 20:09:44 +0200) >> >> are available in the git repository at: >> >> git://github.com/anholt/linux tags/bcm2835-soc-next-2017-08-15 >> >> for you to fetch changes up to 067b437e55a892e3ebb13e40c98825fcfa1e2d99: >> >> ARM: bcm2836: Send event when onlining other cores (2017-08-15 10:52:26 -0700) >> >> ---------------------------------------------------------------- >> This pull request brings in two things. >> >> One is to use sev() to wake up CPUs that might be sleeping when doing >> the custom spin-table boot process in 32-bit mode (new firmware >> versions will have the CPUs sleeping waiting for an event instead of >> just spinning). However, the irqchip maintainer objected to our SMP >> code continuing to live in the driver, so we had to move it to >> platsmp.c, and to do that we needed a new SMP enable-method to the DT >> for the platsmp.c to attach to (thus the DT cross-merge in this PR). >> The platsmp.c patch was acked by irqchip for going through arm-soc. > > This does make us pull quite a lot of changes, how about I just > cherry-pick "ARM: dts: bcm283x: Add 32-bit enable method for SMP" such > that the branch in itself is functional as-is, but we don't pull in > everything else from devicetree/next? Then you get the commit duplicated in the history, which people generally dislike even more. Also, it depends on the arm64->arm move, so you'd need that as well. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 832 bytes Desc: not available URL: From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753244AbdHQQRG (ORCPT ); Thu, 17 Aug 2017 12:17:06 -0400 Received: from anholt.net ([50.246.234.109]:51760 "EHLO anholt.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752704AbdHQQRE (ORCPT ); Thu, 17 Aug 2017 12:17:04 -0400 From: Eric Anholt To: Florian Fainelli , Florian Fainelli Cc: linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan Wahren , bcm-kernel-feedback-list@broadcom.com Subject: Re: [GIT PULL 2/2] bcm2835-soc-next-2017-08-15 In-Reply-To: <36766926-c8d6-b768-59b6-4ff302a6a5ba@gmail.com> References: <20170815180325.12809-1-eric@anholt.net> <20170815180325.12809-2-eric@anholt.net> <36766926-c8d6-b768-59b6-4ff302a6a5ba@gmail.com> User-Agent: Notmuch/0.22.2+1~gb0bcfaa (http://notmuchmail.org) Emacs/24.5.1 (x86_64-pc-linux-gnu) Date: Thu, 17 Aug 2017 09:12:36 -0700 Message-ID: <87valmgoln.fsf@eliezer.anholt.net> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha512; protocol="application/pgp-signature" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Florian Fainelli writes: > On 08/15/2017 11:03 AM, Eric Anholt wrote: >> The following changes since commit f29c256853b7412961d3ee80ca525bd253057= 3db: >>=20 >> ARM: dts: bcm283x: Add 32-bit enable method for SMP (2017-08-14 20:09:= 44 +0200) >>=20 >> are available in the git repository at: >>=20 >> git://github.com/anholt/linux tags/bcm2835-soc-next-2017-08-15 >>=20 >> for you to fetch changes up to 067b437e55a892e3ebb13e40c98825fcfa1e2d99: >>=20 >> ARM: bcm2836: Send event when onlining other cores (2017-08-15 10:52:2= 6 -0700) >>=20 >> ---------------------------------------------------------------- >> This pull request brings in two things. >>=20 >> One is to use sev() to wake up CPUs that might be sleeping when doing >> the custom spin-table boot process in 32-bit mode (new firmware >> versions will have the CPUs sleeping waiting for an event instead of >> just spinning). However, the irqchip maintainer objected to our SMP >> code continuing to live in the driver, so we had to move it to >> platsmp.c, and to do that we needed a new SMP enable-method to the DT >> for the platsmp.c to attach to (thus the DT cross-merge in this PR). >> The platsmp.c patch was acked by irqchip for going through arm-soc. > > This does make us pull quite a lot of changes, how about I just > cherry-pick "ARM: dts: bcm283x: Add 32-bit enable method for SMP" such > that the branch in itself is functional as-is, but we don't pull in > everything else from devicetree/next? Then you get the commit duplicated in the history, which people generally dislike even more. Also, it depends on the arm64->arm move, so you'd need that as well. --=-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE/JuuFDWp9/ZkuCBXtdYpNtH8nugFAlmVwHUACgkQtdYpNtH8 nujiaA//V7U4b/BK79wbZ1j9hCjsqOYleDrq+fq4G1GVBdMSk7g/EGFa6srWd0xN 1gd/dNyqW6/hCjYsA3JPkVL8S5Vd1Hf5gfMZMrM9Hkt118V0vNrBxlkGDOVwMQ0U o8ABwUAGbiu4COS8bE9dL0ZIXOQtKPOWfEdK1TL0I9A+fo89vfC34Dt7xAFH7zgG pFB5JCZJhcnwy/KK2Nxy6SBC+YFPakw+toF+PVElrJJcylh6e2YH37pvfl8N6ZiC tQhywz4Bkgfz6FX/qVjel6sAd0K3ceFKbWwYHwlN2WTjZT5P0UkGFPx5/NMV/gre qVBKMKxUvQcFKKnLLH6/Q25Zu7+8Q0RwkESRQqBuT6+FOA5Ct/RMl6VmRY0TwN2Q Dab5bHfFNV4Jd0yGkY3VHW6ZOyRtIGVqDY9hI94J3JkBJgyv7dEQ1cym7V3mclou LDceAbje0LBrSPL8yD60EOW5l3K/e/uhouOZlpj3rctE2w6i/U7GW1rslpRzE9pC S1b1L+H3XkvgfSWmKJu1ZnnXsnKNNJ/yvx7HTHwPFAzNH+VyoO1pAJyS166U94FC 7Wt69OjmhzsTeEH2rHZbmxtolr6RnAGmN6QdGrdnteQN7o4rKv294SAPXmFiIhyq P4hbKDwiNxYmpzf/xGDzHGY+Dlk+EMlIT/SEbBp5YhSE6nkpBKY= =B1Ud -----END PGP SIGNATURE----- --=-=-=--