diff for duplicates of <87vasbcxq8.fsf@free-electrons.com> diff --git a/a/1.txt b/N1/1.txt index 4ee8b40..8b637ad 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ Hi Chris, - On mar., f?vr. 07 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: + On mar., févr. 07 2017, Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> wrote: > The DFX server on the 98dx3236 and compatible SoCs has an ID register > that provides revision information that the PCI based ID register @@ -14,7 +14,7 @@ Thanks, Gregory -> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> +> Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> > --- > > Notes: @@ -43,7 +43,7 @@ Gregory > +- reg: should be the register base and length as documented in the > + datasheet for the Device ID Status > + -> +soc-id at f8244 { +> +soc-id@f8244 { > + compatible = "marvell,mv98dx3236-soc-id"; > + reg = <0xf8244 0x4>; > +}; @@ -55,12 +55,12 @@ Gregory > ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; > reg = <MBUS_ID(0x08, 0x00) 0 0x100000>; > -> + soc-id at f8244 { +> + soc-id@f8244 { > + compatible = "marvell,mv98dx3236-soc-id"; > + reg = <0xf8244 0x4>; > + }; > + -> dfx_coredivclk: corediv-clock at f8268 { +> dfx_coredivclk: corediv-clock@f8268 { > compatible = "marvell,mv98dx3236-corediv-clock"; > reg = <0xf8268 0xc>; > diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c @@ -146,3 +146,7 @@ Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index bf6b5e2..0a8798e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,14 +1,24 @@ "ref\020170207202815.20226-1-chris.packham@alliedtelesis.co.nz\0" "ref\020170207202815.20226-5-chris.packham@alliedtelesis.co.nz\0" - "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" - "Subject\0[PATCH v2 4/6] ARM: mvebu: Add mv98dx3236-soc-id\0" + "ref\020170207202815.20226-5-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org\0" + "From\0Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Subject\0Re: [PATCH v2 4/6] ARM: mvebu: Add mv98dx3236-soc-id\0" "Date\0Wed, 15 Feb 2017 15:52:47 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>\0" + "Cc\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org> + Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> + Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Hi Chris,\n" " \n" - " On mar., f?vr. 07 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:\n" + " On mar., f\303\251vr. 07 2017, Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> wrote:\n" "\n" "> The DFX server on the 98dx3236 and compatible SoCs has an ID register\n" "> that provides revision information that the PCI based ID register\n" @@ -22,7 +32,7 @@ "\n" "Gregory\n" "\n" - "> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>\n" + "> Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>\n" "> ---\n" ">\n" "> Notes:\n" @@ -51,7 +61,7 @@ "> +- reg: should be the register base and length as documented in the\n" "> + datasheet for the Device ID Status\n" "> +\n" - "> +soc-id at f8244 {\n" + "> +soc-id@f8244 {\n" "> +\tcompatible = \"marvell,mv98dx3236-soc-id\";\n" "> +\treg = <0xf8244 0x4>;\n" "> +};\n" @@ -63,12 +73,12 @@ "> \t\t\tranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;\n" "> \t\t\treg = <MBUS_ID(0x08, 0x00) 0 0x100000>;\n" "> \n" - "> +\t\t\tsoc-id at f8244 {\n" + "> +\t\t\tsoc-id@f8244 {\n" "> +\t\t\t\tcompatible = \"marvell,mv98dx3236-soc-id\";\n" "> +\t\t\t\treg = <0xf8244 0x4>;\n" "> +\t\t\t};\n" "> +\n" - "> \t\t\tdfx_coredivclk: corediv-clock at f8268 {\n" + "> \t\t\tdfx_coredivclk: corediv-clock@f8268 {\n" "> \t\t\t\tcompatible = \"marvell,mv98dx3236-corediv-clock\";\n" "> \t\t\t\treg = <0xf8268 0xc>;\n" "> diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c\n" @@ -153,6 +163,10 @@ "Gregory Clement, Free Electrons\n" "Kernel, drivers, real-time and embedded Linux\n" "development, consulting, training and support.\n" - http://free-electrons.com + "http://free-electrons.com\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -bca8fe0939e8099aa85ec91218b8ccc1e0257495c053130f0bcd395a864d0b6d +98c993f15d1bc814f719c27c9663859d94d100a574ffc7a3b41f7b9d6661fcfd
diff --git a/a/1.txt b/N2/1.txt index 4ee8b40..05b8b87 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,6 +1,6 @@ Hi Chris, - On mar., f?vr. 07 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: + On mar., févr. 07 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > The DFX server on the 98dx3236 and compatible SoCs has an ID register > that provides revision information that the PCI based ID register @@ -43,7 +43,7 @@ Gregory > +- reg: should be the register base and length as documented in the > + datasheet for the Device ID Status > + -> +soc-id at f8244 { +> +soc-id@f8244 { > + compatible = "marvell,mv98dx3236-soc-id"; > + reg = <0xf8244 0x4>; > +}; @@ -55,12 +55,12 @@ Gregory > ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; > reg = <MBUS_ID(0x08, 0x00) 0 0x100000>; > -> + soc-id at f8244 { +> + soc-id@f8244 { > + compatible = "marvell,mv98dx3236-soc-id"; > + reg = <0xf8244 0x4>; > + }; > + -> dfx_coredivclk: corediv-clock at f8268 { +> dfx_coredivclk: corediv-clock@f8268 { > compatible = "marvell,mv98dx3236-corediv-clock"; > reg = <0xf8268 0xc>; > diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c diff --git a/a/content_digest b/N2/content_digest index bf6b5e2..08c1b7e 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,14 +1,23 @@ "ref\020170207202815.20226-1-chris.packham@alliedtelesis.co.nz\0" "ref\020170207202815.20226-5-chris.packham@alliedtelesis.co.nz\0" - "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" - "Subject\0[PATCH v2 4/6] ARM: mvebu: Add mv98dx3236-soc-id\0" + "From\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0" + "Subject\0Re: [PATCH v2 4/6] ARM: mvebu: Add mv98dx3236-soc-id\0" "Date\0Wed, 15 Feb 2017 15:52:47 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Chris Packham <chris.packham@alliedtelesis.co.nz>\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + Rob Herring <robh+dt@kernel.org> + Mark Rutland <mark.rutland@arm.com> + Jason Cooper <jason@lakedaemon.net> + Andrew Lunn <andrew@lunn.ch> + Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + Russell King <linux@armlinux.org.uk> + devicetree@vger.kernel.org + " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" "Hi Chris,\n" " \n" - " On mar., f?vr. 07 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:\n" + " On mar., f\303\251vr. 07 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:\n" "\n" "> The DFX server on the 98dx3236 and compatible SoCs has an ID register\n" "> that provides revision information that the PCI based ID register\n" @@ -51,7 +60,7 @@ "> +- reg: should be the register base and length as documented in the\n" "> + datasheet for the Device ID Status\n" "> +\n" - "> +soc-id at f8244 {\n" + "> +soc-id@f8244 {\n" "> +\tcompatible = \"marvell,mv98dx3236-soc-id\";\n" "> +\treg = <0xf8244 0x4>;\n" "> +};\n" @@ -63,12 +72,12 @@ "> \t\t\tranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;\n" "> \t\t\treg = <MBUS_ID(0x08, 0x00) 0 0x100000>;\n" "> \n" - "> +\t\t\tsoc-id at f8244 {\n" + "> +\t\t\tsoc-id@f8244 {\n" "> +\t\t\t\tcompatible = \"marvell,mv98dx3236-soc-id\";\n" "> +\t\t\t\treg = <0xf8244 0x4>;\n" "> +\t\t\t};\n" "> +\n" - "> \t\t\tdfx_coredivclk: corediv-clock at f8268 {\n" + "> \t\t\tdfx_coredivclk: corediv-clock@f8268 {\n" "> \t\t\t\tcompatible = \"marvell,mv98dx3236-corediv-clock\";\n" "> \t\t\t\treg = <0xf8268 0xc>;\n" "> diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c\n" @@ -155,4 +164,4 @@ "development, consulting, training and support.\n" http://free-electrons.com -bca8fe0939e8099aa85ec91218b8ccc1e0257495c053130f0bcd395a864d0b6d +7cfebff178c8cd05dff2bdcd5616b6f2d5a500e1325a272c51e95cd453e33bf3
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.