From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [kvm-unit-tests PATCH v2 04/10] arm/arm64: add some delay routines Date: Mon, 06 Jun 2016 18:39:50 +0100 Message-ID: <87vb1mgqs9.fsf@linaro.org> References: <1465064165-14885-5-git-send-email-drjones@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E8238410B5 for ; Mon, 6 Jun 2016 13:35:28 -0400 (EDT) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QE2XxERSO76v for ; Mon, 6 Jun 2016 13:35:26 -0400 (EDT) Received: from mail-wm0-f50.google.com (mail-wm0-f50.google.com [74.125.82.50]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 991D140FA6 for ; Mon, 6 Jun 2016 13:35:26 -0400 (EDT) Received: by mail-wm0-f50.google.com with SMTP id k204so36798678wmk.0 for ; Mon, 06 Jun 2016 10:39:36 -0700 (PDT) In-reply-to: <1465064165-14885-5-git-send-email-drjones@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Andrew Jones Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, andre.przywara@arm.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu List-Id: kvmarm@lists.cs.columbia.edu CkFuZHJldyBKb25lcyA8ZHJqb25lc0ByZWRoYXQuY29tPiB3cml0ZXM6Cgo+IEFsbG93IGEgdGhy ZWFkIHRvIHdhaXQgc29tZSBzcGVjaWZpZWQgYW1vdW50IG9mIHRpbWUuIENhbgo+IHNwZWNpZnkg aW4gY3ljbGVzLCB1c2VjcywgYW5kIG1zZWNzLgoKSSB3b25kZXIgaWYgZGVsYXkoKSBhbmQgbWRl bGF5KCkgY2FuIGJlIGluIGNvbW1vbiBjb2RlIHdpdGgganVzdCB0aGUKZnJlcSBhbmQgY291bnQg Z2V0dGluZyBmdW5jdGlvbnMgaW4gc3BlY2lmaWMgY29kZT8gSSBndWVzcyB0aGF0IHdvdWxkCm5l ZWQgYSBsaWIvYXJtLWdlbmVyaWMvIG9yIHNvbWUgc3VjaD8KCk90aGVyd2lzZToKClJldmlld2Vk LWJ5OiBBbGV4IEJlbm7DqWUgPGFsZXguYmVubmVlQGxpbmFyby5vcmc+Cgo+Cj4gU2lnbmVkLW9m Zi1ieTogQW5kcmV3IEpvbmVzIDxkcmpvbmVzQHJlZGhhdC5jb20+Cj4gLS0tCj4gIGxpYi9hcm0v YXNtL3Byb2Nlc3Nvci5oICAgfCAxOSArKysrKysrKysrKysrKysrKysrCj4gIGxpYi9hcm0vcHJv Y2Vzc29yLmMgICAgICAgfCAxNSArKysrKysrKysrKysrKysKPiAgbGliL2FybTY0L2FzbS9wcm9j ZXNzb3IuaCB8IDE5ICsrKysrKysrKysrKysrKysrKysKPiAgbGliL2FybTY0L3Byb2Nlc3Nvci5j ICAgICB8IDE1ICsrKysrKysrKysrKysrKwo+ICA0IGZpbGVzIGNoYW5nZWQsIDY4IGluc2VydGlv bnMoKykKPgo+IGRpZmYgLS1naXQgYS9saWIvYXJtL2FzbS9wcm9jZXNzb3IuaCBiL2xpYi9hcm0v YXNtL3Byb2Nlc3Nvci5oCj4gaW5kZXggZDIwNDhmNWY1ZjdlNi4uYWZjOTAzY2E3ZDRhYiAxMDA2 NDQKPiAtLS0gYS9saWIvYXJtL2FzbS9wcm9jZXNzb3IuaAo+ICsrKyBiL2xpYi9hcm0vYXNtL3By b2Nlc3Nvci5oCj4gQEAgLTUsNyArNSw5IEBACj4gICAqCj4gICAqIFRoaXMgd29yayBpcyBsaWNl bnNlZCB1bmRlciB0aGUgdGVybXMgb2YgdGhlIEdOVSBMR1BMLCB2ZXJzaW9uIDIuCj4gICAqLwo+ ICsjaW5jbHVkZSA8bGliY2ZsYXQuaD4KPiAgI2luY2x1ZGUgPGFzbS9wdHJhY2UuaD4KPiArI2lu Y2x1ZGUgPGFzbS9iYXJyaWVyLmg+Cj4KPiAgZW51bSB2ZWN0b3Igewo+ICAJRVhDUFROX1JTVCwK PiBAQCAtNTEsNCArNTMsMjEgQEAgZXh0ZXJuIGludCBtcGlkcl90b19jcHUodW5zaWduZWQgbG9u ZyBtcGlkcik7Cj4gIGV4dGVybiB2b2lkIHN0YXJ0X3Vzcih2b2lkICgqZnVuYykodm9pZCAqYXJn KSwgdm9pZCAqYXJnLCB1bnNpZ25lZCBsb25nIHNwX3Vzcik7Cj4gIGV4dGVybiBib29sIGlzX3Vz ZXIodm9pZCk7Cj4KPiArc3RhdGljIGlubGluZSB1NjQgZ2V0X2NudHZjdCh2b2lkKQo+ICt7Cj4g Kwl1NjQgdmN0Owo+ICsJaXNiKCk7Cj4gKwlhc20gdm9sYXRpbGUoIm1ycmMgcDE1LCAxLCAlUTAs ICVSMCwgYzE0IiA6ICI9ciIgKHZjdCkpOwo+ICsJcmV0dXJuIHZjdDsKPiArfQo+ICsKPiArZXh0 ZXJuIHZvaWQgZGVsYXkodTY0IGN5Y2xlcyk7Cj4gK2V4dGVybiB2b2lkIHVkZWxheSh1bnNpZ25l ZCBsb25nIHVzZWNzKTsKPiArCj4gK3N0YXRpYyBpbmxpbmUgdm9pZCBtZGVsYXkodW5zaWduZWQg bG9uZyBtc2VjcykKPiArewo+ICsJd2hpbGUgKG1zZWNzLS0pCj4gKwkJdWRlbGF5KDEwMDApOwo+ ICt9Cj4gKwo+ICAjZW5kaWYgLyogX0FTTUFSTV9QUk9DRVNTT1JfSF8gKi8KPiBkaWZmIC0tZ2l0 IGEvbGliL2FybS9wcm9jZXNzb3IuYyBiL2xpYi9hcm0vcHJvY2Vzc29yLmMKPiBpbmRleCA1NGZk Yjg3ZWYwMTk2Li5jMmVlMzYwZGY2ODg0IDEwMDY0NAo+IC0tLSBhL2xpYi9hcm0vcHJvY2Vzc29y LmMKPiArKysgYi9saWIvYXJtL3Byb2Nlc3Nvci5jCj4gQEAgLTksNiArOSw3IEBACj4gICNpbmNs dWRlIDxhc20vcHRyYWNlLmg+Cj4gICNpbmNsdWRlIDxhc20vcHJvY2Vzc29yLmg+Cj4gICNpbmNs dWRlIDxhc20vdGhyZWFkX2luZm8uaD4KPiArI2luY2x1ZGUgPGFzbS9iYXJyaWVyLmg+Cj4KPiAg c3RhdGljIGNvbnN0IGNoYXIgKnByb2Nlc3Nvcl9tb2Rlc1tdID0gewo+ICAJIlVTRVJfMjYiLCAi RklRXzI2IiAsICJJUlFfMjYiICwgIlNWQ18yNiIgLAo+IEBAIC0xNDEsMyArMTQyLDE3IEBAIGJv b2wgaXNfdXNlcih2b2lkKQo+ICB7Cj4gIAlyZXR1cm4gY3VycmVudF90aHJlYWRfaW5mbygpLT5m bGFncyAmIFRJRl9VU0VSX01PREU7Cj4gIH0KPiArCj4gK3ZvaWQgZGVsYXkodTY0IGN5Y2xlcykK PiArewo+ICsJdTY0IHN0YXJ0ID0gZ2V0X2NudHZjdCgpOwo+ICsJd2hpbGUgKChnZXRfY250dmN0 KCkgLSBzdGFydCkgPCBjeWNsZXMpCj4gKwkJY3B1X3JlbGF4KCk7Cj4gK30KPiArCj4gK3ZvaWQg dWRlbGF5KHVuc2lnbmVkIGxvbmcgdXNlYykKPiArewo+ICsJdW5zaWduZWQgaW50IGZycTsKPiAr CWFzbSB2b2xhdGlsZSgibXJjIHAxNSwgMCwgJTAsIGMxNCwgYzAsIDAiIDogIj1yIiAoZnJxKSk7 Cj4gKwlkZWxheSgodTY0KXVzZWMgKiBmcnEgLyAxMDAwMDAwKTsKPiArfQo+IGRpZmYgLS1naXQg YS9saWIvYXJtNjQvYXNtL3Byb2Nlc3Nvci5oIGIvbGliL2FybTY0L2FzbS9wcm9jZXNzb3IuaAo+ IGluZGV4IDdlNDQ4ZGM4MWE2YWEuLjk0ZjdjZTM1YjY1YzEgMTAwNjQ0Cj4gLS0tIGEvbGliL2Fy bTY0L2FzbS9wcm9jZXNzb3IuaAo+ICsrKyBiL2xpYi9hcm02NC9hc20vcHJvY2Vzc29yLmgKPiBA QCAtMTcsOCArMTcsMTAgQEAKPiAgI2RlZmluZSBTQ1RMUl9FTDFfTQkoMSA8PCAwKQo+Cj4gICNp Zm5kZWYgX19BU1NFTUJMWV9fCj4gKyNpbmNsdWRlIDxsaWJjZmxhdC5oPgo+ICAjaW5jbHVkZSA8 YXNtL3B0cmFjZS5oPgo+ICAjaW5jbHVkZSA8YXNtL2Vzci5oPgo+ICsjaW5jbHVkZSA8YXNtL2Jh cnJpZXIuaD4KPgo+ICBlbnVtIHZlY3RvciB7Cj4gIAlFTDFUX1NZTkMsCj4gQEAgLTg5LDUgKzkx LDIyIEBAIGV4dGVybiBpbnQgbXBpZHJfdG9fY3B1KHVuc2lnbmVkIGxvbmcgbXBpZHIpOwo+ICBl eHRlcm4gdm9pZCBzdGFydF91c3Iodm9pZCAoKmZ1bmMpKHZvaWQgKmFyZyksIHZvaWQgKmFyZywg dW5zaWduZWQgbG9uZyBzcF91c3IpOwo+ICBleHRlcm4gYm9vbCBpc191c2VyKHZvaWQpOwo+Cj4g K3N0YXRpYyBpbmxpbmUgdTY0IGdldF9jbnR2Y3Qodm9pZCkKPiArewo+ICsJdTY0IHZjdDsKPiAr CWlzYigpOwo+ICsJYXNtIHZvbGF0aWxlKCJtcnMgJTAsIGNudHZjdF9lbDAiIDogIj1yIiAodmN0 KSk7Cj4gKwlyZXR1cm4gdmN0Owo+ICt9Cj4gKwo+ICtleHRlcm4gdm9pZCBkZWxheSh1NjQgY3lj bGVzKTsKPiArZXh0ZXJuIHZvaWQgdWRlbGF5KHVuc2lnbmVkIGxvbmcgdXNlY3MpOwo+ICsKPiAr c3RhdGljIGlubGluZSB2b2lkIG1kZWxheSh1bnNpZ25lZCBsb25nIG1zZWNzKQo+ICt7Cj4gKwl3 aGlsZSAobXNlY3MtLSkKPiArCQl1ZGVsYXkoMTAwMCk7Cj4gK30KPiArCj4gICNlbmRpZiAvKiAh X19BU1NFTUJMWV9fICovCj4gICNlbmRpZiAvKiBfQVNNQVJNNjRfUFJPQ0VTU09SX0hfICovCj4g ZGlmZiAtLWdpdCBhL2xpYi9hcm02NC9wcm9jZXNzb3IuYyBiL2xpYi9hcm02NC9wcm9jZXNzb3Iu Ywo+IGluZGV4IGRlZWFiNGVjOWM4YWMuLjUwZmE4MzVjNmYxZTMgMTAwNjQ0Cj4gLS0tIGEvbGli L2FybTY0L3Byb2Nlc3Nvci5jCj4gKysrIGIvbGliL2FybTY0L3Byb2Nlc3Nvci5jCj4gQEAgLTks NiArOSw3IEBACj4gICNpbmNsdWRlIDxhc20vcHRyYWNlLmg+Cj4gICNpbmNsdWRlIDxhc20vcHJv Y2Vzc29yLmg+Cj4gICNpbmNsdWRlIDxhc20vdGhyZWFkX2luZm8uaD4KPiArI2luY2x1ZGUgPGFz bS9iYXJyaWVyLmg+Cj4KPiAgc3RhdGljIGNvbnN0IGNoYXIgKnZlY3Rvcl9uYW1lc1tdID0gewo+ ICAJImVsMXRfc3luYyIsCj4gQEAgLTI1MywzICsyNTQsMTcgQEAgYm9vbCBpc191c2VyKHZvaWQp Cj4gIHsKPiAgCXJldHVybiBjdXJyZW50X3RocmVhZF9pbmZvKCktPmZsYWdzICYgVElGX1VTRVJf TU9ERTsKPiAgfQo+ICsKPiArdm9pZCBkZWxheSh1NjQgY3ljbGVzKQo+ICt7Cj4gKwl1NjQgc3Rh cnQgPSBnZXRfY250dmN0KCk7Cj4gKwl3aGlsZSAoKGdldF9jbnR2Y3QoKSAtIHN0YXJ0KSA8IGN5 Y2xlcykKPiArCQljcHVfcmVsYXgoKTsKPiArfQo+ICsKPiArdm9pZCB1ZGVsYXkodW5zaWduZWQg bG9uZyB1c2VjKQo+ICt7Cj4gKwl1bnNpZ25lZCBpbnQgZnJxOwo+ICsJYXNtIHZvbGF0aWxlKCJt cnMgJTAsIGNudGZycV9lbDAiIDogIj1yIiAoZnJxKSk7Cj4gKwlkZWxheSgodTY0KXVzZWMgKiBm cnEgLyAxMDAwMDAwKTsKPiArfQoKCi0tCkFsZXggQmVubsOpZQpfX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fXwprdm1hcm0gbWFpbGluZyBsaXN0Cmt2bWFybUBs aXN0cy5jcy5jb2x1bWJpYS5lZHUKaHR0cHM6Ly9saXN0cy5jcy5jb2x1bWJpYS5lZHUvbWFpbG1h bi9saXN0aW5mby9rdm1hcm0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g8sm15284013wme.23.2016.06.06.10.39.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Jun 2016 10:39:34 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTPS id 0B5583E02BF; Mon, 6 Jun 2016 18:39:50 +0100 (BST) User-agent: mu4e 0.9.17; emacs 25.0.94.5 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Andrew Jones Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andre.przywara@arm.com, peter.maydell@linaro.org, christoffer.dall@linaro.org, marc.zyngier@arm.com Subject: Re: [kvm-unit-tests PATCH v2 04/10] arm/arm64: add some delay routines In-reply-to: <1465064165-14885-5-git-send-email-drjones@redhat.com> Date: Mon, 06 Jun 2016 18:39:50 +0100 Message-ID: <87vb1mgqs9.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-TUID: EDXV9vlOoDgn Andrew Jones writes: > Allow a thread to wait some specified amount of time. Can > specify in cycles, usecs, and msecs. I wonder if delay() and mdelay() can be in common code with just the freq and count getting functions in specific code? I guess that would need a lib/arm-generic/ or some such? Otherwise: Reviewed-by: Alex Bennée > > Signed-off-by: Andrew Jones > --- > lib/arm/asm/processor.h | 19 +++++++++++++++++++ > lib/arm/processor.c | 15 +++++++++++++++ > lib/arm64/asm/processor.h | 19 +++++++++++++++++++ > lib/arm64/processor.c | 15 +++++++++++++++ > 4 files changed, 68 insertions(+) > > diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h > index d2048f5f5f7e6..afc903ca7d4ab 100644 > --- a/lib/arm/asm/processor.h > +++ b/lib/arm/asm/processor.h > @@ -5,7 +5,9 @@ > * > * This work is licensed under the terms of the GNU LGPL, version 2. > */ > +#include > #include > +#include > > enum vector { > EXCPTN_RST, > @@ -51,4 +53,21 @@ extern int mpidr_to_cpu(unsigned long mpidr); > extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); > extern bool is_user(void); > > +static inline u64 get_cntvct(void) > +{ > + u64 vct; > + isb(); > + asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (vct)); > + return vct; > +} > + > +extern void delay(u64 cycles); > +extern void udelay(unsigned long usecs); > + > +static inline void mdelay(unsigned long msecs) > +{ > + while (msecs--) > + udelay(1000); > +} > + > #endif /* _ASMARM_PROCESSOR_H_ */ > diff --git a/lib/arm/processor.c b/lib/arm/processor.c > index 54fdb87ef0196..c2ee360df6884 100644 > --- a/lib/arm/processor.c > +++ b/lib/arm/processor.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > static const char *processor_modes[] = { > "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , > @@ -141,3 +142,17 @@ bool is_user(void) > { > return current_thread_info()->flags & TIF_USER_MODE; > } > + > +void delay(u64 cycles) > +{ > + u64 start = get_cntvct(); > + while ((get_cntvct() - start) < cycles) > + cpu_relax(); > +} > + > +void udelay(unsigned long usec) > +{ > + unsigned int frq; > + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); > + delay((u64)usec * frq / 1000000); > +} > diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h > index 7e448dc81a6aa..94f7ce35b65c1 100644 > --- a/lib/arm64/asm/processor.h > +++ b/lib/arm64/asm/processor.h > @@ -17,8 +17,10 @@ > #define SCTLR_EL1_M (1 << 0) > > #ifndef __ASSEMBLY__ > +#include > #include > #include > +#include > > enum vector { > EL1T_SYNC, > @@ -89,5 +91,22 @@ extern int mpidr_to_cpu(unsigned long mpidr); > extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); > extern bool is_user(void); > > +static inline u64 get_cntvct(void) > +{ > + u64 vct; > + isb(); > + asm volatile("mrs %0, cntvct_el0" : "=r" (vct)); > + return vct; > +} > + > +extern void delay(u64 cycles); > +extern void udelay(unsigned long usecs); > + > +static inline void mdelay(unsigned long msecs) > +{ > + while (msecs--) > + udelay(1000); > +} > + > #endif /* !__ASSEMBLY__ */ > #endif /* _ASMARM64_PROCESSOR_H_ */ > diff --git a/lib/arm64/processor.c b/lib/arm64/processor.c > index deeab4ec9c8ac..50fa835c6f1e3 100644 > --- a/lib/arm64/processor.c > +++ b/lib/arm64/processor.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > static const char *vector_names[] = { > "el1t_sync", > @@ -253,3 +254,17 @@ bool is_user(void) > { > return current_thread_info()->flags & TIF_USER_MODE; > } > + > +void delay(u64 cycles) > +{ > + u64 start = get_cntvct(); > + while ((get_cntvct() - start) < cycles) > + cpu_relax(); > +} > + > +void udelay(unsigned long usec) > +{ > + unsigned int frq; > + asm volatile("mrs %0, cntfrq_el0" : "=r" (frq)); > + delay((u64)usec * frq / 1000000); > +} -- Alex Bennée From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9yV8-0005vo-6G for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:39:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9yV1-0002DG-Q1 for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:39:45 -0400 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:36157) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9yV1-0002D4-Fo for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:39:39 -0400 Received: by mail-wm0-x235.google.com with SMTP id n184so103252666wmn.1 for ; Mon, 06 Jun 2016 10:39:39 -0700 (PDT) From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1465064165-14885-5-git-send-email-drjones@redhat.com> Date: Mon, 06 Jun 2016 18:39:50 +0100 Message-ID: <87vb1mgqs9.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [kvm-unit-tests PATCH v2 04/10] arm/arm64: add some delay routines List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andrew Jones Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andre.przywara@arm.com, peter.maydell@linaro.org, christoffer.dall@linaro.org, marc.zyngier@arm.com Andrew Jones writes: > Allow a thread to wait some specified amount of time. Can > specify in cycles, usecs, and msecs. I wonder if delay() and mdelay() can be in common code with just the freq and count getting functions in specific code? I guess that would need a lib/arm-generic/ or some such? Otherwise: Reviewed-by: Alex Bennée > > Signed-off-by: Andrew Jones > --- > lib/arm/asm/processor.h | 19 +++++++++++++++++++ > lib/arm/processor.c | 15 +++++++++++++++ > lib/arm64/asm/processor.h | 19 +++++++++++++++++++ > lib/arm64/processor.c | 15 +++++++++++++++ > 4 files changed, 68 insertions(+) > > diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h > index d2048f5f5f7e6..afc903ca7d4ab 100644 > --- a/lib/arm/asm/processor.h > +++ b/lib/arm/asm/processor.h > @@ -5,7 +5,9 @@ > * > * This work is licensed under the terms of the GNU LGPL, version 2. > */ > +#include > #include > +#include > > enum vector { > EXCPTN_RST, > @@ -51,4 +53,21 @@ extern int mpidr_to_cpu(unsigned long mpidr); > extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); > extern bool is_user(void); > > +static inline u64 get_cntvct(void) > +{ > + u64 vct; > + isb(); > + asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (vct)); > + return vct; > +} > + > +extern void delay(u64 cycles); > +extern void udelay(unsigned long usecs); > + > +static inline void mdelay(unsigned long msecs) > +{ > + while (msecs--) > + udelay(1000); > +} > + > #endif /* _ASMARM_PROCESSOR_H_ */ > diff --git a/lib/arm/processor.c b/lib/arm/processor.c > index 54fdb87ef0196..c2ee360df6884 100644 > --- a/lib/arm/processor.c > +++ b/lib/arm/processor.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > static const char *processor_modes[] = { > "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , > @@ -141,3 +142,17 @@ bool is_user(void) > { > return current_thread_info()->flags & TIF_USER_MODE; > } > + > +void delay(u64 cycles) > +{ > + u64 start = get_cntvct(); > + while ((get_cntvct() - start) < cycles) > + cpu_relax(); > +} > + > +void udelay(unsigned long usec) > +{ > + unsigned int frq; > + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); > + delay((u64)usec * frq / 1000000); > +} > diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h > index 7e448dc81a6aa..94f7ce35b65c1 100644 > --- a/lib/arm64/asm/processor.h > +++ b/lib/arm64/asm/processor.h > @@ -17,8 +17,10 @@ > #define SCTLR_EL1_M (1 << 0) > > #ifndef __ASSEMBLY__ > +#include > #include > #include > +#include > > enum vector { > EL1T_SYNC, > @@ -89,5 +91,22 @@ extern int mpidr_to_cpu(unsigned long mpidr); > extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); > extern bool is_user(void); > > +static inline u64 get_cntvct(void) > +{ > + u64 vct; > + isb(); > + asm volatile("mrs %0, cntvct_el0" : "=r" (vct)); > + return vct; > +} > + > +extern void delay(u64 cycles); > +extern void udelay(unsigned long usecs); > + > +static inline void mdelay(unsigned long msecs) > +{ > + while (msecs--) > + udelay(1000); > +} > + > #endif /* !__ASSEMBLY__ */ > #endif /* _ASMARM64_PROCESSOR_H_ */ > diff --git a/lib/arm64/processor.c b/lib/arm64/processor.c > index deeab4ec9c8ac..50fa835c6f1e3 100644 > --- a/lib/arm64/processor.c > +++ b/lib/arm64/processor.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > static const char *vector_names[] = { > "el1t_sync", > @@ -253,3 +254,17 @@ bool is_user(void) > { > return current_thread_info()->flags & TIF_USER_MODE; > } > + > +void delay(u64 cycles) > +{ > + u64 start = get_cntvct(); > + while ((get_cntvct() - start) < cycles) > + cpu_relax(); > +} > + > +void udelay(unsigned long usec) > +{ > + unsigned int frq; > + asm volatile("mrs %0, cntfrq_el0" : "=r" (frq)); > + delay((u64)usec * frq / 1000000); > +} -- Alex Bennée