Re: [Intel-gfx] [PATCH] i915: Set ddi_pll_sel in DP MST path

[Jani Nikula <jani.nikula@linux.intel.com>]

On Mon, 31 Aug 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Aug 31, 2015 at 11:23:28AM +0300, Ander Conselvan de Oliveira wrote:
>> The DP MST encoder config function never sets ddi_pll_sel, even though
>> its value is programmed in its ->pre_enable() hook. That used to work
>> because a new pipe_config was kzalloc'ed at every modeset, and the value
>> of zero selects the highest clock for the PLL. Starting with the commit
>> below, the value of ddi_pll_sel is preserved through modesets, and since
>> the correct value wasn't properly setup by the MST code, it could lead
>> to warnings and blank screens.
>
> The ddi pll handling is still quite a mess. Every platform does things
> just a bit different to the next guy.
>
> But yeah, looks like HSW/BDW handle the PLL selection for DP from
> the encoder .compute_config() so MST should do the same since it
> (re)computes the main link config for each stream. And SKL and BXT
> handle DP via the .crtc_compute_clock() path, so nothing needed for
> them I suppose.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pushed to drm-intel-next-fixes, thanks for the patch and review.

I cherry-picked

commit 840b32b7eda7837db6e0236293f71fc6644dedf8
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Tue Aug 11 20:21:46 2015 +0300

    drm/i915: Don't use link_bw for PLL setup

from drm-intel-next-queued first to avoid conflicts.

BR,
Jani.


>
>> 
>> commit 8504c74c7ae48b4b8ed1f1c0acf67482a7f45c93
>> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
>> Date:   Fri May 15 11:51:50 2015 +0300
>> 
>>     drm/i915: Preserve ddi_pll_sel when allocating new pipe_config
>> 
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91628
>> Cc: stable@vger.kernel.org
>> Cc: Timo Aaltonen <tjaalton@ubuntu.com>
>> Cc: Luciano Coelho <luciano.coelho@intel.com>
>> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c     | 2 +-
>>  drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
>>  drivers/gpu/drm/i915/intel_drv.h    | 1 +
>>  3 files changed, 7 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 9e90a2b..393aed0 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1190,7 +1190,7 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>>  	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
>>  }
>>  
>> -static void
>> +void
>>  hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
>>  {
>>  	memset(&pipe_config->dpll_hw_state, 0,
>> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
>> index ebf2054..677d70e 100644
>> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
>> @@ -33,6 +33,7 @@
>>  static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>>  					struct intel_crtc_state *pipe_config)
>>  {
>> +	struct drm_device *dev = encoder->base.dev;
>>  	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
>>  	struct intel_digital_port *intel_dig_port = intel_mst->primary;
>>  	struct intel_dp *intel_dp = &intel_dig_port->dp;
>> @@ -88,6 +89,10 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>>  			       &pipe_config->dp_m_n);
>>  
>>  	pipe_config->dp_m_n.tu = slots;
>> +
>> +	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>> +		hsw_dp_set_ddi_pll_sel(pipe_config);
>> +
>>  	return true;
>>  
>>  }
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index c61ba47..458f56c 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1209,6 +1209,7 @@ void intel_edp_drrs_disable(struct intel_dp *intel_dp);
>>  void intel_edp_drrs_invalidate(struct drm_device *dev,
>>  		unsigned frontbuffer_bits);
>>  void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
>> +void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
>>  
>>  /* intel_dp_mst.c */
>>  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
>> -- 
>> 2.4.3
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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-- 
Jani Nikula, Intel Open Source Technology Center