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* [PATCH] [trivial] drm/i915: Convert straggling MCHBAR registers
@ 2013-10-23  5:05 Ben Widawsky
  2013-10-23  6:54 ` Jani Nikula
  0 siblings, 1 reply; 3+ messages in thread
From: Ben Widawsky @ 2013-10-23  5:05 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky

All our registers which are written through the MCHBAR are defined
descriptively as an offset to the MCHBAR. We had 3 outliers here.
Convert these as well so all registers which are offsets are MCHBAR can
be easily identified/found within the code.

With this, convert DCLK to also follow this format.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b4f7b1..6c98238 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1480,7 +1480,7 @@
 #define MCHBAR_MIRROR_BASE_SNB	0x140000
 
 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
-#define DCLK 0x5e04
+#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
 
 /** 915-945 and GM965 MCH register controlling DRAM channel access */
 #define DCC			0x10200
@@ -1775,9 +1775,9 @@
 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
 
-#define GEN6_GT_PERF_STATUS	0x145948
-#define GEN6_RP_STATE_LIMITS	0x145994
-#define GEN6_RP_STATE_CAP	0x145998
+#define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)
+#define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
+#define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
 
 /*
  * Logical Context regs
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3e140ab..d4dd543 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3915,7 +3915,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
 	/* Convert from kHz to MHz */
 	max_ia_freq /= 1000;
 
-	min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
+	min_ring_freq = I915_READ(DCLK) & 0xf;
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
-- 
1.8.4.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] [trivial] drm/i915: Convert straggling MCHBAR registers
  2013-10-23  5:05 [PATCH] [trivial] drm/i915: Convert straggling MCHBAR registers Ben Widawsky
@ 2013-10-23  6:54 ` Jani Nikula
  2013-10-27 13:39   ` Daniel Vetter
  0 siblings, 1 reply; 3+ messages in thread
From: Jani Nikula @ 2013-10-23  6:54 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky

On Wed, 23 Oct 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> All our registers which are written through the MCHBAR are defined
> descriptively as an offset to the MCHBAR. We had 3 outliers here.
> Convert these as well so all registers which are offsets are MCHBAR can
> be easily identified/found within the code.
>
> With this, convert DCLK to also follow this format.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2b4f7b1..6c98238 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1480,7 +1480,7 @@
>  #define MCHBAR_MIRROR_BASE_SNB	0x140000
>  
>  /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
> -#define DCLK 0x5e04
> +#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
>  
>  /** 915-945 and GM965 MCH register controlling DRAM channel access */
>  #define DCC			0x10200
> @@ -1775,9 +1775,9 @@
>  #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
>  #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
>  
> -#define GEN6_GT_PERF_STATUS	0x145948
> -#define GEN6_RP_STATE_LIMITS	0x145994
> -#define GEN6_RP_STATE_CAP	0x145998
> +#define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> +#define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
> +#define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
>  
>  /*
>   * Logical Context regs
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3e140ab..d4dd543 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3915,7 +3915,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
>  	/* Convert from kHz to MHz */
>  	max_ia_freq /= 1000;
>  
> -	min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
> +	min_ring_freq = I915_READ(DCLK) & 0xf;
>  	/* convert DDR frequency from units of 266.6MHz to bandwidth */
>  	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
>  
> -- 
> 1.8.4.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] [trivial] drm/i915: Convert straggling MCHBAR registers
  2013-10-23  6:54 ` Jani Nikula
@ 2013-10-27 13:39   ` Daniel Vetter
  0 siblings, 0 replies; 3+ messages in thread
From: Daniel Vetter @ 2013-10-27 13:39 UTC (permalink / raw)
  To: Jani Nikula; +Cc: Intel GFX, Ben Widawsky, Ben Widawsky

On Wed, Oct 23, 2013 at 09:54:41AM +0300, Jani Nikula wrote:
> On Wed, 23 Oct 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> > All our registers which are written through the MCHBAR are defined
> > descriptively as an offset to the MCHBAR. We had 3 outliers here.
> > Convert these as well so all registers which are offsets are MCHBAR can
> > be easily identified/found within the code.
> >
> > With this, convert DCLK to also follow this format.
> >
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2013-10-27 13:39 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2013-10-23  5:05 [PATCH] [trivial] drm/i915: Convert straggling MCHBAR registers Ben Widawsky
2013-10-23  6:54 ` Jani Nikula
2013-10-27 13:39   ` Daniel Vetter

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