From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RUIRO-0000i7-QE for qemu-devel@nongnu.org; Sat, 26 Nov 2011 08:37:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RUIRN-00008q-6D for qemu-devel@nongnu.org; Sat, 26 Nov 2011 08:37:14 -0500 Received: from mail-ww0-f53.google.com ([74.125.82.53]:36446) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RUIRM-00008k-Rg for qemu-devel@nongnu.org; Sat, 26 Nov 2011 08:37:13 -0500 Received: by wwf10 with SMTP id 10so4741812wwf.10 for ; Sat, 26 Nov 2011 05:37:11 -0800 (PST) From: Richard Sandiford Date: Sat, 26 Nov 2011 13:37:07 +0000 Message-ID: <87vcq7ngxo.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: [Qemu-devel] [PATCH] mips: Fix BC1ANY[24]F instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is. Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests. Signed-off-by: Richard Sandiford --- target-mips/translate.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index ba45eb0..2b977b3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -6017,7 +6017,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); - tcg_gen_nor_i32(t0, t0, t1); + tcg_gen_nand_i32(t0, t0, t1); tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); @@ -6041,11 +6041,11 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); - tcg_gen_nor_i32(t0, t0, t1); + tcg_gen_nand_i32(t0, t0, t1); tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); -- 1.7.2.5